{"title":"带有1.2 mw双向收发器的8gbps低延迟多滴片上传输线互连","authors":"H. Ito, M. Kimura, K. Okada, K. Masu","doi":"10.1109/VLSIC.2007.4342688","DOIUrl":null,"url":null,"abstract":"This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers\",\"authors\":\"H. Ito, M. Kimura, K. Okada, K. Masu\",\"doi\":\"10.1109/VLSIC.2007.4342688\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342688\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342688","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers
This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.
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