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2007 IEEE Symposium on VLSI Circuits最新文献

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Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC 移动多媒体SoC中具有共享L1缓存的同质双处理器核心
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342724
M. Nakajima, T. Yamamoto, M. Yamasaki, K. Kaneko, T. Hosoki
{"title":"Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC","authors":"M. Nakajima, T. Yamamoto, M. Yamasaki, K. Kaneko, T. Hosoki","doi":"10.1109/VLSIC.2007.4342724","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342724","url":null,"abstract":"We propose a novel dual-processor core which adopts a shared L1 cache with active way scheme. In this scheme, each WAY of cache is owned by specific processor and replace operation is only happened to its own WAYs. This architecture only requires dual port TAG, and no dual port DATA memory to realize simultaneous access from both processors, and can guarantee no cache thrashing and no snoop overhead. And also by sharing cache memory and cache controller, power dissipation is 23% smaller in case of heavy load and area is 29 % smaller than dual processor core with snoop cache.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125531448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 70nm 16Gb 16-level-cell NAND Flash Memory 70nm 16Gb 16级单元NAND闪存
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342710
N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, H. Nakai
{"title":"A 70nm 16Gb 16-level-cell NAND Flash Memory","authors":"N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, H. Nakai","doi":"10.1109/VLSIC.2007.4342710","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342710","url":null,"abstract":"A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A Trimming-Free CMOS Bandgap-Reference Circuit with Sub-1-V-Supply Voltage Operation 一种工作电压低于1 v的无滤波CMOS带隙参考电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342675
Y. Okuda, T. Tsukamoto, M. Hiraki, M. Horiguchi, T. Ito
{"title":"A Trimming-Free CMOS Bandgap-Reference Circuit with Sub-1-V-Supply Voltage Operation","authors":"Y. Okuda, T. Tsukamoto, M. Hiraki, M. Horiguchi, T. Ito","doi":"10.1109/VLSIC.2007.4342675","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342675","url":null,"abstract":"We propose a bandgap-reference circuit (BGR) that is very robust against voltage, temperature, and local device variations and features sub-l-V operation. The BGR achieves \"3sigma = 2.5%\" accuracy for local variation and operates at a 0.95-V-supply voltage.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122284399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 21-GHz Fractional-N Synthesizer in 130-nm CMOS 130nm CMOS的21ghz分数n合成器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342744
Yanping Ding, K. O. Kenneth
{"title":"A 21-GHz Fractional-N Synthesizer in 130-nm CMOS","authors":"Yanping Ding, K. O. Kenneth","doi":"10.1109/VLSIC.2007.4342744","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342744","url":null,"abstract":"A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125626527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A very wideband fully balanced active RC polyphase filter based on CMOS inverters in 0.18μm CMOS technology 一种基于0.18μm CMOS逆变器的宽带全平衡有源RC多相滤波器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342676
K. Komoriyama, E. Yoshida, M. Yashiki, H. Tanimoto
{"title":"A very wideband fully balanced active RC polyphase filter based on CMOS inverters in 0.18μm CMOS technology","authors":"K. Komoriyama, E. Yoshida, M. Yashiki, H. Tanimoto","doi":"10.1109/VLSIC.2007.4342676","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342676","url":null,"abstract":"A very wideband active RC polyphase filter(RCPF) is presented. A unit active RCPF section structure is an ordinary RCPF followed by opamps with parallel RC feedback. The cascaded sections allow zeros and poles to set independently, it can greatly reduce the element value spread. A six-stage active RCPF with a relative bandwidth of 100(=100 MHz/1 MHz) was fabricated by 0.18 μm CMOS with novel fully differential OTAs consisting only of CMOS inverters. Measured frequency responses closely matched simulated results.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133113866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Single-Photon Avalanche Diode Imager for Fluorescence Lifetime Applications 用于荧光寿命应用的单光子雪崩二极管成像仪
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342691
D. E. Schwartz, E. Charbon, Kenneth L. Shepard
{"title":"A Single-Photon Avalanche Diode Imager for Fluorescence Lifetime Applications","authors":"D. E. Schwartz, E. Charbon, Kenneth L. Shepard","doi":"10.1109/VLSIC.2007.4342691","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342691","url":null,"abstract":"A 64-by-64-pixel CMOS single-photon avalanche diode (SPAD) imager for time-resolved fluorescence detection features actively quenched and reset pixels, allowing gated detection to eliminate pile-up nonlinearities common to most time-correlated single-photon counting (TCSPC) approaches. Timing information is collected using an on-chip time-to-digital converter (TDC) based on a counter and a supply-regulated delay-locked loop (DLL).","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS 14gb /s 32 mW交流耦合90纳米CMOS接收器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342754
M. Hossain, A. C. Carusone
{"title":"A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS","authors":"M. Hossain, A. C. Carusone","doi":"10.1109/VLSIC.2007.4342754","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342754","url":null,"abstract":"This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133680078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Dual Threshold Preamplifier and Multi-Channel DSP for Human Factored Digital Hearing Aid Chip 人因数字助听器芯片的双阈值前置放大器和多通道DSP
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342679
Sunyoung Kim, Seung Jin Lee, Namjun Cho, Seong-Jun Song, H. Yoo
{"title":"Dual Threshold Preamplifier and Multi-Channel DSP for Human Factored Digital Hearing Aid Chip","authors":"Sunyoung Kim, Seung Jin Lee, Namjun Cho, Seong-Jun Song, H. Yoo","doi":"10.1109/VLSIC.2007.4342679","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342679","url":null,"abstract":"The low-power, high-programmability digital hearing aid chip with consideration of human factors is implemented. To achieve the human factored design with low-power consumption, the dual threshold preamplifier and the multi-channel digital signal processor (DSP) are designed. The dynamic range of the dual threshold preamplifier exists from 0.45-V to 0.8-V and dissipates 32-muW from a single 0.9-V supply. The core area of the preamplifier and the DSP are 0.057-mm2 and 0.5-mm2 respectively in a 0.18-mum CMOS technology.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122228556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS 90nm CMOS的6位3.5 gs /s 0.9 v 98 mw Flash ADC
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342767
K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki
{"title":"A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS","authors":"K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki","doi":"10.1109/VLSIC.2007.4342767","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342767","url":null,"abstract":"A 6-bit 3.5-GS/s flash ADC is fabricated in a 90nm CMOS process. A clamp diode with a replica biasing and an acceleration capacitor are introduced for high-speed overdrive recovery. Averaging network is analyzed to explore the effect of tail current mismatch. The 3.5-GS/s ADC consumes 98mW with 0.9V power supply. Its SNDR is 31.18dB with Nyquist frequency input.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123651848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Notice of Violation of IEEE Publication Principles0.13μ CMOS hybrid TV tuner using a calibrated image and harmonic rejection mixer 0.13μ CMOS混合电视调谐器使用经过校准的图像和谐波抑制混频器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342720
A. Maxim, R. Johns, S. Dupue
{"title":"Notice of Violation of IEEE Publication Principles0.13μ CMOS hybrid TV tuner using a calibrated image and harmonic rejection mixer","authors":"A. Maxim, R. Johns, S. Dupue","doi":"10.1109/VLSIC.2007.4342720","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342720","url":null,"abstract":"A high image (65dB) and harmonic (70dB) rejection single conversion tuner was realized in 0.13μm CMOS for hybrid analog-digital TV receivers. The different local oscillator phases required to drive the harmonic rejection mixer were obtained with an analog phase interpolator connected at the output of a multi-phase ring-oscillator. The image rejection is calibrated by injecting a test tone and shifting the Q LO clocks till a minimum output power is achieved. Tuner specifications include: <7dB noise figure, 45dB max gain for analog TV and 115dB gain for digital TV, >5 dBm out of band IIP3, <0.8°rms integrated phase noise, <-80dBc spurs, 1.3W power from a dual 1.8/3.3V supply and 3mm2 die area.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122457047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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