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2007 IEEE Symposium on VLSI Circuits最新文献

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A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos 一个10位20MHz 38mW 950MHz CT ΣΔ ADC，带有5位噪声整形vco量化器和0.13u cmos的DEM电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342737
M. Straayer, M. Perrott
{"title":"A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos","authors":"M. Straayer, M. Perrott","doi":"10.1109/VLSIC.2007.4342737","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342737","url":null,"abstract":"A combined 5-bit, 1st order noise-shaped quantizer and DEM circuit running at 950MHz based on a multi-phase VCO is presented. This quantizer structure is the key element in a 3rd order noise shaped ADC with 2nd order loop dynamics and a single opamp. Measured performance is 60dB SNR at 20MHz bandwidth in 0.13u CMOS while consuming 32mA from a 1.2V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126379469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond 一种用于Sub-40nm MLC NAND闪存及更先进存储器的具有临时LSB存储方案的零元间干扰页架构
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342709
Ki-Tae Park
{"title":"A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond","authors":"Ki-Tae Park","doi":"10.1109/VLSIC.2007.4342709","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342709","url":null,"abstract":"A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124068476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application 用于低功耗多相锁相环的多相输出电平移位系统
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342729
A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, S. Dosho
{"title":"Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application","authors":"A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, S. Dosho","doi":"10.1109/VLSIC.2007.4342729","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342729","url":null,"abstract":"Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LSs) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LSs with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1 mA at 123 MHz and accomplishes 63-phase accuracy of 0.5LSB.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
BER-based Adaptation of I/O Link Equalizers 基于ber的I/O链路均衡器自适应
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342756
Ehung Chen, Jihong Ren, J. Zerbe, B. Leibowitz, Haechang Lee, V. Stojanović, C. Yang
{"title":"BER-based Adaptation of I/O Link Equalizers","authors":"Ehung Chen, Jihong Ren, J. Zerbe, B. Leibowitz, Haechang Lee, V. Stojanović, C. Yang","doi":"10.1109/VLSIC.2007.4342756","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342756","url":null,"abstract":"Many equalization techniques have been demonstrated for multi-Gb/s I/O transceivers in order to compensate for the limited bandwidth of the communication medium. Since the performance of links is typically defined by the bit-error-rate (BER), this paper proposes a new adaptation method using the BER as the objective function to maximize the receiver voltage margin. Measurement results compare the new algorithm with commonly used sign-sign least mean square (SS-LMS) adaptation. The results show significant improvement when applied to a transmitter FIR equalizer with peak power constraint, and modest improvement when used in a receiver DFE.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132771695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.016mm2, 2.4GHz RF signal quality measurement macro for RF test and diagnosis 一个0.016mm2, 2.4GHz射频信号质量测量宏，用于射频测试和诊断
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342723
K. Nose, M. Mizuno
{"title":"A 0.016mm2, 2.4GHz RF signal quality measurement macro for RF test and diagnosis","authors":"K. Nose, M. Mizuno","doi":"10.1109/VLSIC.2007.4342723","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342723","url":null,"abstract":"Our RF signal-quality measurement macro employs 1) the new window-shifting measurement technique, which can obtain power of high-frequency component with lower-frequency measurements, and 2) the new stair-like weighted addition technique, which can decrease the error due to harmonic power of measured signals. The macro was only 1/10 area of conventional spectrum analyzers. Carrier power of 2.4 GHz-Tx with the measurement error of <1dB was measured without RF-testers, and harmonic-emission exceeding FCC regulations (>-20dBm) were successfully detected.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS 在65nm CMOS中工作电压低至0.41V的5.3GHz 8T-SRAM
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342739
Leland Chang, Yutaka Nakamura, R. Montoye, J. Sawada, Andrew K. Martin, Kiyofumi Kinoshita, Fadi H. Gebara, Kanak B. Agarwal, D. Acharyya, Wilfried Haensch, Kohji Hosokawa, D. Jamsek
{"title":"A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS","authors":"Leland Chang, Yutaka Nakamura, R. Montoye, J. Sawada, Andrew K. Martin, Kiyofumi Kinoshita, Fadi H. Gebara, Kanak B. Agarwal, D. Acharyya, Wilfried Haensch, Kohji Hosokawa, D. Jamsek","doi":"10.1109/VLSIC.2007.4342739","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342739","url":null,"abstract":"A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
1 Gbit/s bidirectional full-wire rate communication LSI for residential gateways 1gbit /s双向全线速率通信LSI，用于住宅网关
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342689
Yukikuni Nishidat, Kenji Kawait, Keiichi Koiket, Katsuichi Oyamat, Tetsuo Hayashi, Hiroyuki Nouchi
{"title":"1 Gbit/s bidirectional full-wire rate communication LSI for residential gateways","authors":"Yukikuni Nishidat, Kenji Kawait, Keiichi Koiket, Katsuichi Oyamat, Tetsuo Hayashi, Hiroyuki Nouchi","doi":"10.1109/VLSIC.2007.4342689","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342689","url":null,"abstract":"A communication LSI for residential gateways has been developed. The LSI has an inline-IPsec circuit, which achieves 1 Gbit/s performance for both encryption and decryption, a small-scale high-speed look-up circuit in which only comparators are made parallel, and a hierarchical and reconfigurable QoS circuit. A 2 Gbit/s full wire rate throughput was achieved at a power consumption of 2 W.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133953691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS 用于5Gbps PCI Express Gen2多通道串行链路接收器的双PFD相位旋转多相锁相环(0.13um CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342732
Sungjoon Kim, Dongyun Lee, Young-Soo Park, Yongsam Moon, Daeyun Shim
{"title":"A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS","authors":"Sungjoon Kim, Dongyun Lee, Young-Soo Park, Yongsam Moon, Daeyun Shim","doi":"10.1109/VLSIC.2007.4342732","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342732","url":null,"abstract":"A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5 Gbps serial link receiver is demonstrated using 0.13 mum CMOS. The PLL's 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is achieved by adding only one additional phase-frequency detector (PFD) and a charge pump. The rms jitter is 1.2 ps for 5 Gbps serial link operation. The new PLL occupies 0.015 mm2 and consumes 3 mA from a 1.2 V supply. The small area and low power nature of the architecture is suitable for receivers in multi-lane serial links.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125192272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor Sub-200mV, 3.5pJ/inst, 11nW亚阈值处理器的性能和可变性优化策略
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342694
S. Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, M. Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, D. Sylvester, D. Blaauw
{"title":"Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor","authors":"S. Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, M. Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2007.4342694","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342694","url":null,"abstract":"A robust, energy efficient subthreshold (sub-V<sub>th</sub>) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at V<sub>dd</sub> = 160 mV and 3.5 pJ/inst at V<sub>dd</sub> = 350 mV. Variability and performance optimization techniques are investigated for sub-V<sub>th</sub> circuits.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding 支持54x AAC-LC立体声编码的芯片上的异构多处理器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342719
M. Ito, T. Todaka, T. Tsunoda, H. Tanaka, T. Kodama, H. Shikano, M. Onouchi, K. Uchiyama, T. Odaka, T. Kamei, E. Nagahama, M. Kusaoke, Y. Nitta, Y. Wada, K. Kimura, H. Kasahara
{"title":"Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding","authors":"M. Ito, T. Todaka, T. Tsunoda, H. Tanaka, T. Kodama, H. Shikano, M. Onouchi, K. Uchiyama, T. Odaka, T. Kamei, E. Nagahama, M. Kusaoke, Y. Nitta, Y. Wada, K. Kimura, H. Kasahara","doi":"10.1109/VLSIC.2007.4342719","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342719","url":null,"abstract":"A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has been enabled with 2 DRPs at 300 MHz and 2 CPUs at 600 MHz.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127101160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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