Leland Chang, Yutaka Nakamura, R. Montoye, J. Sawada, Andrew K. Martin, Kiyofumi Kinoshita, Fadi H. Gebara, Kanak B. Agarwal, D. Acharyya, Wilfried Haensch, Kohji Hosokawa, D. Jamsek
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A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41 V at 295 MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8 T cell, 5.3 GHz operation at 1.2 V is achieved.
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