一种用于Sub-40nm MLC NAND闪存及更先进存储器的具有临时LSB存储方案的零元间干扰页架构

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342709

Ki-Tae Park

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引用次数: 18

摘要

提出了一种具有临时LSB存储程序方案的新页面架构，作为亚40nm FG(浮栅)MLC NAND闪存及其他闪存的突破性解决方案。在没有程序速度下降的情况下，该方法能够消除100%的BL -cell和近50%的WL -cell耦合干扰，这是众所周知的FG NAND闪存最关键的缩放障碍。

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A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond

A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.

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2007 IEEE Symposium on VLSI Circuits

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