M. Ito, T. Todaka, T. Tsunoda, H. Tanaka, T. Kodama, H. Shikano, M. Onouchi, K. Uchiyama, T. Odaka, T. Kamei, E. Nagahama, M. Kusaoke, Y. Nitta, Y. Wada, K. Kimura, H. Kasahara
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Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding
A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has been enabled with 2 DRPs at 300 MHz and 2 CPUs at 600 MHz.
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