Sub-200mV, 3.5pJ/inst, 11nW亚阈值处理器的性能和可变性优化策略

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342694

S. Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, M. Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, D. Sylvester, D. Blaauw

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引用次数: 81

摘要

设计了一种鲁棒、节能的亚阈值(sub-Vth)处理器，并以0.13 μ m的技术进行了测试。处理器在Vdd = 160 mV时消耗11 nW，在Vdd = 350 mV时消耗3.5 pJ/inst。研究了亚v次电路的变异性和性能优化技术。

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Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor

A robust, energy efficient subthreshold (sub-V_th) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at V_dd = 160 mV and 3.5 pJ/inst at V_dd = 350 mV. Variability and performance optimization techniques are investigated for sub-V_th circuits.

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2007 IEEE Symposium on VLSI Circuits

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