A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond

Abstract

A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.