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2007 IEEE Symposium on VLSI Circuits最新文献

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A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors 一种用于超低功耗单片移动处理器的1.92 μs唤醒时间厚栅氧化电源开关技术
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342685
K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi, T. Sasaki, T. Kuraishi, Y. Yasu, K. Ishibashi
{"title":"A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors","authors":"K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi, T. Sasaki, T. Kuraishi, Y. Yasu, K. Ishibashi","doi":"10.1109/VLSIC.2007.4342685","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342685","url":null,"abstract":"A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128331392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping 用于片上电源谐振阻尼的开关去耦电容电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342684
J. Gu, Hanyong Eom, C. Kim
{"title":"A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping","authors":"J. Gu, Hanyong Eom, C. Kim","doi":"10.1109/VLSIC.2007.4342684","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342684","url":null,"abstract":"A low power switched decoupling capacitor circuit is proposed to suppress on-chip resonant supply noise. Compared to previous analog techniques, the proposed digital implementation achieves a 9X reduction in quiescent power with improved tolerance to PVT variation and tuning capability for optimal switching threshold. Measurements from a 0.13 mum test chip show an 11X boost in effective decap value and a 9.8 dB suppression in resonant supply noise by using the proposed circuit.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130907661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM 基于处理器的90纳米二极管开关PRAM内置自优化器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342707
Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo, Seungjoon Lee, Woo-Yeong Cho, Bo-Tak Lim, B. Choi, Chang-Sik Kim, C. Kwak, Chang-Hyun Kim, H. Yoo
{"title":"Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM","authors":"Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo, Seungjoon Lee, Woo-Yeong Cho, Bo-Tak Lim, B. Choi, Chang-Sik Kim, C. Kwak, Chang-Hyun Kim, H. Yoo","doi":"10.1109/VLSIC.2007.4342707","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342707","url":null,"abstract":"A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134265325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
1-cc Computer: Cross-Layer Integration with 3.4-nW/bps Link and 22-cm Locationing 1-cc计算机:3.4 nw /bps链路和22厘米定位的跨层集成
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342778
G. Ono, T. Nakagawa, R. Fujiwara, T. Norimatsu, T. Terada, M. Miyazaki, K. Suzuki, K. Yano, Y. Ogata, A. Macki, S. Kobayashi, N. Koshizuka, K. Sakamura
{"title":"1-cc Computer: Cross-Layer Integration with 3.4-nW/bps Link and 22-cm Locationing","authors":"G. Ono, T. Nakagawa, R. Fujiwara, T. Norimatsu, T. Terada, M. Miyazaki, K. Suzuki, K. Yano, Y. Ogata, A. Macki, S. Kobayashi, N. Koshizuka, K. Sakamura","doi":"10.1109/VLSIC.2007.4342778","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342778","url":null,"abstract":"The first 1-cc computer (OCCC) which integrates a sensor, a wireless transceiver, a computing engine and a battery is demonstrated. Cross-layer innovation includes SPIKE control, which achieves record-low 3.4-nW/bps power with 3-ms UWB current control (one order lower than those of reported). Another proposal is communication-location integration (CLI), which achieves 22-cm location accuracy with 1.3% area overhead. Fabricated OCCC is verified to operate as designed.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
High Performance Processor Development for Consumer Electronics Game Processor Perspective 面向消费电子游戏处理器的高性能处理器开发
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342680
J. Brown
{"title":"High Performance Processor Development for Consumer Electronics Game Processor Perspective","authors":"J. Brown","doi":"10.1109/VLSIC.2007.4342680","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342680","url":null,"abstract":"The development of customized solutions for optimized consumer electronics applications like game processors is pushing the boundaries of VLSI in many ways. The author will describe architectural, circuit, packaging and manufacturing challenges focusing on why game processors are different and require unique solutions. A historical perspective of gaming and entertainment systems and their intersection with leading edge processor design will provide insight into future trends and needs in VLSI design.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133569572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mobile Terminals toward LTE and Requirements on Device Technologies 面向LTE的移动终端及设备技术要求
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342673
S. Maruyama, S. Ogawa, K. Chiba
{"title":"Mobile Terminals toward LTE and Requirements on Device Technologies","authors":"S. Maruyama, S. Ogawa, K. Chiba","doi":"10.1109/VLSIC.2007.4342673","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342673","url":null,"abstract":"This paper overviews the universal mobile telecommunications system long term evolution (LTE) and discusses the requirements for device technologies pertaining to mobile terminals. The LTE represents the next generation cellular phone technology that is intended to achieve a high peak data rate, low latency, and high radio efficiency in addition to low cost and sufficiently high mobility characteristics. Vigorous discussion regarding the specifications for LTE is currently ongoing in the 3rd generation partnership project. This paper also introduces various device technologies that support current mobile terminals.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment 分布式交换机环境下面向面积感知低压的8T-SRAM设计
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342741
Y. Morita, H. Fujiwara, Hiroki Noguchi, Y. Iguchi, Koji Nii, H. Kawaguchi, M. Yoshimoto
{"title":"An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment","authors":"Y. Morita, H. Fujiwara, Hiroki Noguchi, Y. Iguchi, Koji Nii, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/VLSIC.2007.4342741","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342741","url":null,"abstract":"This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"23 259","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131692012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 159
A 19-mode 8.29mm2 52-mW LDPC Decoder Chipp for IEEE 802.16e System 用于IEEE 802.16e系统的19模8.29mm2 52-mW LDPC解码器芯片
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342718
Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, A. Wu
{"title":"A 19-mode 8.29mm2 52-mW LDPC Decoder Chipp for IEEE 802.16e System","authors":"Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, A. Wu","doi":"10.1109/VLSIC.2007.4342718","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342718","url":null,"abstract":"This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power consumption. The core area is 4.45 mm2 and the die area is 8.29 mm2.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127990863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS 1.35 GS/s, 10b, 175mw时间交错AD转换器，0.13 μm CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342766
S. Louwsma, E. van Tuijl, M. Vertregt, B. Nauta
{"title":"A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS","authors":"S. Louwsma, E. van Tuijl, M. Vertregt, B. Nauta","doi":"10.1109/VLSIC.2007.4342766","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342766","url":null,"abstract":"A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs 先进嵌入式ram中中子诱导SEU增加多比特故障率的研究
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342774
G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer
{"title":"Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs","authors":"G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer","doi":"10.1109/VLSIC.2007.4342774","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342774","url":null,"abstract":"This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132215453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
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