发布求助
文献互助 智能选刊 最新文献

2007 IEEE Symposium on VLSI Circuits最新文献

筛选
英文 中文
An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations 最小能量运行的最佳电源电压测定电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342696
Y. Ikenaga, M. Nomura, Y. Nakazawa, Y. Hagihara
{"title":"An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations","authors":"Y. Ikenaga, M. Nomura, Y. Nakazawa, Y. Hagihara","doi":"10.1109/VLSIC.2007.4342696","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342696","url":null,"abstract":"We have developed a circuit for determining an optimal supply voltage, VOPT for which energy consumption in circuit operations will be minimized in devices suffering from high-leakage. This VOPT is determined on the basis of a trade-off between power consumption and delay time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines VOPT within 3% of actual minimum energy consumption. VOPT operations with power gating at 40 MHz, and where VDD=0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency).","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124800390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Timing Orthogonal Capacitance Multiplication Technique for PLL 锁相环的定时正交电容倍增技术
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342698
Ping-Ying Wang, Shang-Ping Chen, P. Chen
{"title":"Timing Orthogonal Capacitance Multiplication Technique for PLL","authors":"Ping-Ying Wang, Shang-Ping Chen, P. Chen","doi":"10.1109/VLSIC.2007.4342698","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342698","url":null,"abstract":"In this paper, a timing orthogonal capacitance multiplication technique for PLL is proposed. Its advantages include: 1) Having a flexible, digitally programmable capacitance multiplication factor; 2) Not using op-amps, which reduces the noise contribution and is beneficial in aggressively scaled CMOS technology; and 3) Lowering cost through capacitance area reduction. At 800 MHz, a PLL using this technique consumes 3.3 mW from a 2.5 V supply and achieves <0.5% TOSC RMS jitter. Its performance is comparable to the state-of-the-art while occupying only 125 mum times 100 mum, roughly 1/18 to 1/2 the area reported in recent publications.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115574863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
0.0234mm2/1mW DCO Based Clock/Data Recovery for Gbit/s Applications 0.0234mm2/1mW基于DCO的时钟/数据恢复，用于Gbit/s应用
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342686
Kuan-Hua Chao, Ping-Ying Wang, Tse-Hsiang Hsu
{"title":"0.0234mm2/1mW DCO Based Clock/Data Recovery for Gbit/s Applications","authors":"Kuan-Hua Chao, Ping-Ying Wang, Tse-Hsiang Hsu","doi":"10.1109/VLSIC.2007.4342686","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342686","url":null,"abstract":"A digital controlled oscillator (DCO) based clock and data recovery (CDR) circuit with mixed mode loop filter is designed and fabricated. It is composed of a digital loop filter, a DCO and an analog feed-forward charge-pump to take both advantages of digital and analog design which are 1) small area and low power 2) low latency 3) insensitive to gate oxide leakage in deep submicron process 4) good PSRR (0.447%/V). The circuit is fabricated in a 90 nm CMOS process. The core area is 0.0234 mm2, and the power consumption is less than 1mW when operating at 1.5 Gbps.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116885816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Split 2-0 MASH with Dual Digital Error Correction 一个分裂的2-0 MASH与双数字纠错
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342735
Zhenyong Zhang, J. Steensgaard, G. Temes, Jian-Yi Wu
{"title":"A Split 2-0 MASH with Dual Digital Error Correction","authors":"Zhenyong Zhang, J. Steensgaard, G. Temes, Jian-Yi Wu","doi":"10.1109/VLSIC.2007.4342735","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342735","url":null,"abstract":"A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 mum process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126568651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A CMOS ΔΣ fractional-n frequency synthesizer with quantization noise pushing technique 一种采用量化噪声推进技术的CMOS ΔΣ分数n频率合成器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342743
Yu-Che Yang, Shey-Shi Lu
{"title":"A CMOS ΔΣ fractional-n frequency synthesizer with quantization noise pushing technique","authors":"Yu-Che Yang, Shey-Shi Lu","doi":"10.1109/VLSIC.2007.4342743","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342743","url":null,"abstract":"A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129439500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 108/98 pJ/b 1Gbps Fully Integrated Interference Tolerant Frequency Channelized UWB Transmitter/Receiver 一种108/98 pJ/b 1Gbps全集成抗干扰信道化超宽带发射/接收系统
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342765
A. Medi, W. Namgoong
{"title":"A 108/98 pJ/b 1Gbps Fully Integrated Interference Tolerant Frequency Channelized UWB Transmitter/Receiver","authors":"A. Medi, W. Namgoong","doi":"10.1109/VLSIC.2007.4342765","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342765","url":null,"abstract":"A pulse-based UWB transceiver operating in the 3.25-4.75 GHz band is implemented in 0.18 mum CMOS technology. At 1 Gbps data rate, it dissipates 98mW (98pJ/b) in the receive-mode and 108mW (108pJ/b) in the transmit-mode while achieving a combined Tx/Rx EVM of -32dB. The receiver provides maximum gain of 82dB, 4.5-5.4dB NF, -5 to -10dBm IIP3, and 47dB channel to channel isolation. The transmitter delivers output swing of 800mVpp to 50-ohm load at rates as high as 1.5Gsps.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123781214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS 一个可扩展的5-15Gbps, 14-75mW的低功耗I/O收发器在65nm CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342746
G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O’Mahony, B. Casper, R. Mooney
{"title":"A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS","authors":"G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O’Mahony, B. Casper, R. Mooney","doi":"10.1109/VLSIC.2007.4342746","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342746","url":null,"abstract":"This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8\" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme 一个1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM，具有地址排队方案和Bang-Bang减少抖动的DLL方案
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342706
Yang Ki Kim, Y. Jeon, B. Jeong, N-W. Heo, Soobong Chang, Hangyun Jung, Doo Young Kim, Hoeju Chung, C. Kim, Seung-Bum Ko, K. Kyung, Jei-Hwan Yoo, Sooin Cho
{"title":"A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme","authors":"Yang Ki Kim, Y. Jeon, B. Jeong, N-W. Heo, Soobong Chang, Hangyun Jung, Doo Young Kim, Hoeju Chung, C. Kim, Seung-Bum Ko, K. Kyung, Jei-Hwan Yoo, Sooin Cho","doi":"10.1109/VLSIC.2007.4342706","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342706","url":null,"abstract":"A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80 nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18 mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132616049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 24Gb/s Software Programmable Multi-Channel Transmitter 一个24Gb/s软件可编程多通道发射机
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342757
A. Amirkhany, A. Abbasfar, Jafar Savoj, M. Jeeradit, B. Garlepp, Vladimir Stojanovic, Mark Horowitz
{"title":"A 24Gb/s Software Programmable Multi-Channel Transmitter","authors":"A. Amirkhany, A. Abbasfar, Jafar Savoj, M. Jeeradit, B. Garlepp, Vladimir Stojanovic, Mark Horowitz","doi":"10.1109/VLSIC.2007.4342757","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342757","url":null,"abstract":"A 24Gb/s transmitter with a digital linear equalizer is implemented in 90 nm CMOS technology. It supports 4-channel Analog Multi-Tone (AMT) transmission, where each channel supports 3 GSym/Sec 4 PAM data, as well as a variety of baseband (BB) modes ranging from 2 PAM to 256 PAM. The transmitter operates at maximum rate of 24 Gb/s, dissipating 51 OmW of power in 0.8 mm2","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132291826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Fast-locking Hybrid PLL Synthesizer Combining Integer & Fractional Divisions 结合整数和分数除法的快速锁定混合锁相环合成器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342742
K. Woo, Yong Liu, D. Ham
{"title":"Fast-locking Hybrid PLL Synthesizer Combining Integer & Fractional Divisions","authors":"K. Woo, Yong Liu, D. Ham","doi":"10.1109/VLSIC.2007.4342742","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342742","url":null,"abstract":"This paper reports a single-loop PLL that operates wide-bandwidth fractional-N mode(without any fractional spur reduction circuits) during transient and in a narrow-bandwidth integer-N mode in locked state. This hybrid operation executed via a simple reconfiguration of the single-loop attains both fast locking and design simplicity, a combination that has been previously difficult to achieve. The frequency division mode switching allows the loop bandwidth switching to be performed in a more digital fashion which increases the degree of design freedom for bandwidth switching. A 2.4GHz CMOS prototype synthesizer with a 1MHz resolution performing the hybrid operation has a 20mus lock time for a 64MHz frequency jump, which is 4 times faster than its fixed integer-N operation.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信