Timing Orthogonal Capacitance Multiplication Technique for PLL

Abstract

In this paper, a timing orthogonal capacitance multiplication technique for PLL is proposed. Its advantages include: 1) Having a flexible, digitally programmable capacitance multiplication factor; 2) Not using op-amps, which reduces the noise contribution and is beneficial in aggressively scaled CMOS technology; and 3) Lowering cost through capacitance area reduction. At 800 MHz, a PLL using this technique consumes 3.3 mW from a 2.5 V supply and achieves <0.5% TOSC RMS jitter. Its performance is comparable to the state-of-the-art while occupying only 125 mum times 100 mum, roughly 1/18 to 1/2 the area reported in recent publications.