一个1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM，具有地址排队方案和Bang-Bang减少抖动的DLL方案

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342706

Yang Ki Kim, Y. Jeon, B. Jeong, N-W. Heo, Soobong Chang, Hangyun Jung, Doo Young Kim, Hoeju Chung, C. Kim, Seung-Bum Ko, K. Kyung, Jei-Hwan Yoo, Sooin Cho

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引用次数: 6

摘要

采用80nm双聚CMOS工艺，开发了1.6Gb/s/引脚1Gb DDR3 SDRAM，在1.5 V时CAS延迟为8，消耗30ma IDD2N和160ma IDD4R。通过地址排队方案和自定时IOSA, IDD4R电流可减少18 mA。为了实现1.6Gb/s/引脚操作，使用了一个带有分相插值器的无抖动DLL。

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A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme

A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80 nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18 mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.

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来源期刊

2007 IEEE Symposium on VLSI Circuits

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