{"title":"一种采用量化噪声推进技术的CMOS ΔΣ分数n频率合成器","authors":"Yu-Che Yang, Shey-Shi Lu","doi":"10.1109/VLSIC.2007.4342743","DOIUrl":null,"url":null,"abstract":"A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A CMOS ΔΣ fractional-n frequency synthesizer with quantization noise pushing technique\",\"authors\":\"Yu-Che Yang, Shey-Shi Lu\",\"doi\":\"10.1109/VLSIC.2007.4342743\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342743\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
采用0.18 μ m CMOS技术实现了一种ΔΣ分数n频率合成器和量化噪声推进技术。该技术可将带内相位噪声降低12 dB，将ΔΣ调制器贡献的带外相位噪声降低15 dB以上。2V电源的功耗为26.8mW。
A CMOS ΔΣ fractional-n frequency synthesizer with quantization noise pushing technique
A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.
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