G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O’Mahony, B. Casper, R. Mooney
{"title":"一个可扩展的5-15Gbps, 14-75mW的低功耗I/O收发器在65nm CMOS","authors":"G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O’Mahony, B. Casper, R. Mooney","doi":"10.1109/VLSIC.2007.4342746","DOIUrl":null,"url":null,"abstract":"This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8\" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"131 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"38","resultStr":"{\"title\":\"A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS\",\"authors\":\"G. Balamurugan, J. Kennedy, G. Banerjee, J. Jaussi, M. Mansuri, F. O’Mahony, B. Casper, R. Mooney\",\"doi\":\"10.1109/VLSIC.2007.4342746\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8\\\" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"131 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"38\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342746\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342746","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS
This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
