一个分裂的2-0 MASH与双数字纠错

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342735

Zhenyong Zhang, J. Steensgaard, G. Temes, Jian-Yi Wu

{"title":"一个分裂的2-0 MASH与双数字纠错","authors":"Zhenyong Zhang, J. Steensgaard, G. Temes, Jian-Yi Wu","doi":"10.1109/VLSIC.2007.4342735","DOIUrl":null,"url":null,"abstract":"A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 mum process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A Split 2-0 MASH with Dual Digital Error Correction\",\"authors\":\"Zhenyong Zhang, J. Steensgaard, G. Temes, Jian-Yi Wu\",\"doi\":\"10.1109/VLSIC.2007.4342735\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 mum process.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342735\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

实现了一种双路2-0级联(MASH) ADC，对DAC错误和MASH失配错误进行了快速数字校正。分裂结构允许快速收敛和提高精度的校正。该原型芯片采用CMOS 0.18工艺，采用20 MHz时钟，在1.25 MHz信号频带内实现84 dB动态范围。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Split 2-0 MASH with Dual Digital Error Correction

A dual-path 2-0 cascaded (MASH) ADC was implemented with fast digital correction of both DAC errors and MASH mismatch errors. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18 mum process.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2007 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量