Yang Ki Kim, Y. Jeon, B. Jeong, N-W. Heo, Soobong Chang, Hangyun Jung, Doo Young Kim, Hoeju Chung, C. Kim, Seung-Bum Ko, K. Kyung, Jei-Hwan Yoo, Sooin Cho
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引用次数: 6
Abstract
A 1.6Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80 nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With an address queuing scheme and a self-timed IOSA, IDD4R current can be reduced by 18 mA. To achieve 1.6Gb/s/pin operation, a bang-bang jitter free DLL with a split phase interpolator is employed.