0.0234mm2/1mW DCO Based Clock/Data Recovery for Gbit/s Applications

Abstract

A digital controlled oscillator (DCO) based clock and data recovery (CDR) circuit with mixed mode loop filter is designed and fabricated. It is composed of a digital loop filter, a DCO and an analog feed-forward charge-pump to take both advantages of digital and analog design which are 1) small area and low power 2) low latency 3) insensitive to gate oxide leakage in deep submicron process 4) good PSRR (0.447%/V). The circuit is fabricated in a 90 nm CMOS process. The core area is 0.0234 mm2, and the power consumption is less than 1mW when operating at 1.5 Gbps.