A Scalable 5-15Gbps, 14-75mW Low Power I/O Transceiver in 65nm CMOS

Abstract

This paper presents a scalable low power I/O transceiver in 65 nm CMOS capable of 5-15 Gbps operation over 8" FR4 with power efficiencies between 3-5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power. Low power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low noise offset-calibrated receivers.