An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

Abstract

This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.