基于处理器的90纳米二极管开关PRAM内置自优化器

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342707

Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo, Seungjoon Lee, Woo-Yeong Cho, Bo-Tak Lim, B. Choi, Chang-Sik Kim, C. Kwak, Chang-Hyun Kim, H. Yoo

{"title":"基于处理器的90纳米二极管开关PRAM内置自优化器","authors":"Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo, Seungjoon Lee, Woo-Yeong Cho, Bo-Tak Lim, B. Choi, Chang-Sik Kim, C. Kwak, Chang-Hyun Kim, H. Yoo","doi":"10.1109/VLSIC.2007.4342707","DOIUrl":null,"url":null,"abstract":"A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM\",\"authors\":\"Kyomin Sohn, Hyejung Kim, Jerald Yoo, Jeong-Ho Woo, Seungjoon Lee, Woo-Yeong Cho, Bo-Tak Lim, B. Choi, Chang-Sik Kim, C. Kwak, Chang-Hyun Kim, H. Yoo\",\"doi\":\"10.1109/VLSIC.2007.4342707\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342707\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342707","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

PRAM包括8b嵌入式RISC，用于生成优化的内部时序和电压参数，以控制电池电阻的变化。采用基于处理器的内置自优化器(BISO)检测、分析和控制具有小单元电阻裕度窗口的PRAM块。采用90nm三金属二极管开关PRAM电池技术制备了4mb测试PRAM。测量的利润率增加了221%。

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Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM

A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.

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来源期刊

2007 IEEE Symposium on VLSI Circuits

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