Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342774

G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer

引用次数: 46

Abstract

This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.

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先进嵌入式ram中中子诱导SEU增加多比特故障率的研究

本文报道了在65nm三井嵌入式sram中，由于中子诱导的单事件扰动(SEU)，大大增加了多比特故障率。在详细的故障模式分析和电路仿真的基础上，建立了一种新的故障模型，并推导了宽松的ECC准则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 IEEE Symposium on VLSI Circuits

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