A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342766

S. Louwsma, E. van Tuijl, M. Vertregt, B. Nauta

引用次数: 40

Abstract

A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.

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1.35 GS/s, 10b, 175mw时间交错AD转换器，0.13 μm CMOS

提出了一个具有16个通道的时间交错ADC，每个通道由两个连续近似(SA) ADC组成。提出了三种提高SA-ADC速度的技术。在输入频率为4ghz时，单通道性能为6.9 ENOB。多通道性能为7.7 ENOB, 1.35 GS/s, ERBW为1 GHz, FoM为0.6 pJ/转换步长。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 IEEE Symposium on VLSI Circuits

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