先进嵌入式ram中中子诱导SEU增加多比特故障率的研究

G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer
{"title":"先进嵌入式ram中中子诱导SEU增加多比特故障率的研究","authors":"G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer","doi":"10.1109/VLSIC.2007.4342774","DOIUrl":null,"url":null,"abstract":"This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"46","resultStr":"{\"title\":\"Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs\",\"authors\":\"G. Georgakos, P. Huber, M. Ostermayr, E. Amirante, F. Ruckerbauer\",\"doi\":\"10.1109/VLSIC.2007.4342774\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"46\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342774\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 46

摘要

本文报道了在65nm三井嵌入式sram中,由于中子诱导的单事件扰动(SEU),大大增加了多比特故障率。在详细的故障模式分析和电路仿真的基础上,建立了一种新的故障模型,并推导了宽松的ECC准则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs
This paper reports a dramatically increased multi-bit failure rate due to neutron induced single event upset (SEU) in 65 nm triple-well embedded SRAMs. Based on detailed fail-pattern analysis and circuit simulation a novel failure model is developed and relaxed ECC guidelines are derived.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信