用于IEEE 802.16e系统的19模8.29mm2 52-mW LDPC解码器芯片

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342718

Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, A. Wu

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引用次数: 19

摘要

本文提出了一种支持IEEE 802.16e系统全部19种模式的LDPC解码器芯片。提出了一种有效的设计策略，可将解码延迟降低31.25%，并将硬件利用率从50%提高到75%。此外，我们还提出了一种可以动态调整迭代次数的提前终止方案。该多模芯片的最大测量频率为83.3 MHz，功耗仅为52 mW。芯面积4.45 mm2，模面积8.29 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 19-mode 8.29mm2 52-mW LDPC Decoder Chipp for IEEE 802.16e System

This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power consumption. The core area is 4.45 mm2 and the die area is 8.29 mm2.

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2007 IEEE Symposium on VLSI Circuits

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