90nm CMOS的6位3.5 gs /s 0.9 v 98 mw Flash ADC

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342767

K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki

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引用次数: 31

摘要

采用90nm CMOS工艺制作了一个6位3.5 gs /s闪存ADC。介绍了一种具有复制偏置的箝位二极管和一个加速电容，用于高速超速恢复。分析了平均网络对尾电流失配的影响。3.5-GS/s ADC在0.9V电源下功耗98mW。其SNDR为31.18dB，输入奈奎斯特频率。

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A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS

A 6-bit 3.5-GS/s flash ADC is fabricated in a 90nm CMOS process. A clamp diode with a replica biasing and an acceleration capacitor are introduced for high-speed overdrive recovery. Averaging network is analyzed to explore the effect of tail current mismatch. The 3.5-GS/s ADC consumes 98mW with 0.9V power supply. Its SNDR is 31.18dB with Nyquist frequency input.

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2007 IEEE Symposium on VLSI Circuits

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