70nm 16Gb 16级单元NAND闪存

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342710

N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, K. Kanazawa, K. Imamiya, H. Nakai

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引用次数: 47

摘要

采用70nm设计规则开发了16gb 16级单元(16LC) NAND快闪存储器。这种16LC NAND闪存可以在一个单元中存储4位，与具有相同设计规则的4级单元(4LC) NAND闪存相比，可以实现两倍的比特密度。新的编程方法实现了0.62 MB/s的编程吞吐量。

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A 70nm 16Gb 16-level-cell NAND Flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.

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2007 IEEE Symposium on VLSI Circuits

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