{"title":"130nm CMOS的21ghz分数n合成器","authors":"Yanping Ding, K. O. Kenneth","doi":"10.1109/VLSIC.2007.4342744","DOIUrl":null,"url":null,"abstract":"A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 21-GHz Fractional-N Synthesizer in 130-nm CMOS\",\"authors\":\"Yanping Ding, K. O. Kenneth\",\"doi\":\"10.1109/VLSIC.2007.4342744\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342744\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.
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