14gb /s 32 mW交流耦合90纳米CMOS接收器

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342754

M. Hossain, A. C. Carusone

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引用次数: 10

摘要

本文介绍了一种用于高密度互连的高速交流耦合接收机结构。该架构结合了一种新颖的迟滞电路路径和线性宽带放大器路径，以从80-fF电容耦合通道中恢复NRZ信号。使用这种双路技术，90纳米CMOS原型在1.2 v电源消耗32 mW的情况下实现了14gb /s的运行。该接收机的测量灵敏度优于100 mVp-p差分。

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A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS

This paper introduces a high-speed AC coupled receiver architecture for high density interconnects. The proposed architecture combines a novel hysteresis circuit path and a linear broadband amplifier path to recover a NRZ signal from an 80-fF capacitively coupled channel. Using this dual path technique, a 90-nm CMOS prototype achieves 14-Gb/s operation while consuming 32 mW from a 1.2-V supply. The measured sensitivity of the receiver is better than 100 mVp-p differential.

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2007 IEEE Symposium on VLSI Circuits

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