An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342683

Y. Nakamura, M. Takamiya, T. Sakurai

引用次数: 1

Abstract

An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.

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一种用于纳秒级电源噪声的片上高压电源消声器

针对纳秒级电源噪声，提出了一种采用高压供电线路的片上消声器。该消噪器采用90纳米CMOS工艺，降噪68%，功耗提高2.0%。在相同降噪条件下，消去器的面积损失分别是片上附加去耦电容器和供电线路面积损失的1/77和1/45。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2007 IEEE Symposium on VLSI Circuits

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