用于移动应用的2.8至67.2mW低功耗和功耗感知H.264编码器

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342727

Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Shao-Yi Chien, Liang-Gee Chen

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引用次数: 42

摘要

一个2.8至67.2 mW的H.264编码器实现在一个12.8 mm2的芯片上，采用0.18 μ m的CMOS技术。所提出的并行架构以及快速算法和数据重用方案可以节省77.9%的功耗。电源感知是通过灵活的系统层次结构提供的，该系统层次结构支持内容感知算法和模块门控时钟。

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2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications

A 2.8 to 67.2 mW H.264 encoder is implemented on a 12.8 mm2 die with 0.18 mum CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.

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2007 IEEE Symposium on VLSI Circuits

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