{"title":"带片上环传递功能校准电路的PVT容限锁相环","authors":"M. Kondou, T. Mori","doi":"10.1109/VLSIC.2007.4342731","DOIUrl":null,"url":null,"abstract":"A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function is presented. Test chips with 9 conditions, MOSes, resistors and capacitors, were fabricated in a 90 nm CMOS technology. Experimental results show that the phase noise remains + 2dBc/Hz within 10 MHz offset under any PVT condition.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit\",\"authors\":\"M. Kondou, T. Mori\",\"doi\":\"10.1109/VLSIC.2007.4342731\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function is presented. Test chips with 9 conditions, MOSes, resistors and capacitors, were fabricated in a 90 nm CMOS technology. Experimental results show that the phase noise remains + 2dBc/Hz within 10 MHz offset under any PVT condition.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342731\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit
A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function is presented. Test chips with 9 conditions, MOSes, resistors and capacitors, were fabricated in a 90 nm CMOS technology. Experimental results show that the phase noise remains + 2dBc/Hz within 10 MHz offset under any PVT condition.
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