A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores

Abstract

This paper describes a parity-checking fault-tolerant adder designed for 6.5 GHz operation with total power consumption of 54 mW, targeted for 65 nm 64-bit microprocessor execution cores. The adder is fully self-checking and guarantees 100% coverage of single-faults (including multi-bit output errors originating from single-faults) on any sequential/combinational node in the design. The sparse-tree design enables partial pre-computation of the critical carry-parities, resulting in 33% reduction in parity-computation delay overhead with a low 6% area overhead for fault-detection.