一个12gs /s相位校准CMOS数模转换器

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342769

J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, B. Garlepp

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引用次数: 9

摘要

一个12gs /s的8位数模转换器(DAC)可以通过传统的背板通道实现24gb /s的信令。该电路采用90 nm CMOS工艺设计，面积为670 μ m × 350μ m, INL和DNL分别为0.31和0.28 LSB。实测SNDR和SFDR在750 MHz时分别为41 dB和51 dB，在1.5 GHz时分别为32.5 dB和35 dB。1v和1.8 v电源的功耗为190mw。

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A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter

A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

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2007 IEEE Symposium on VLSI Circuits

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