A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator

Abstract

A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.