Daeik D. Kim, Jonghae Kim, J. Plouchart, Choongyeun Cho, D. Lim, Weipeng Li, R. Trzcinski
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引用次数: 5
摘要
采用65nm SOI CMOS技术集成了一个75GHz锁相环前端，由互补LC压控振荡器、带交流耦合的缓冲器和静态CML锁存分压器组成。该电路是根据毫米波链路规格、技术考虑、工艺变化和拓扑选择开发的。锁相环前端以73.4GHz为中心实现5.9%的调谐范围，在10MHz偏移71mW时自由运行相位噪声为-1 lOdBc/Hz。
A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology
A 75GHz PLL front-end, composed of complementary LC VCO, a buffer with AC coupling, and a static CML latch divider, is integrated in 65 nm SOI CMOS technology. The circuitry is developed with milli-meter wave link specifications, technology consideration, process variation, and topology selections. The PLL front-end achieves 5.9% tuning range centered at 73.4GHz and free-running phase noise of -1 lOdBc/Hz at 10MHz offset with 71mW.
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