{"title":"基于6Snm CMOS的11gb /s 2.4 mW半速率双抽头DFE接收机","authors":"A. Rylyakov","doi":"10.1109/VLSIC.2007.4342747","DOIUrl":null,"url":null,"abstract":"A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10-14 with a PRBS7 test sequence passing through a 30\" channel (15dB of loss at 5.5GHz).","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS\",\"authors\":\"A. Rylyakov\",\"doi\":\"10.1109/VLSIC.2007.4342747\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10-14 with a PRBS7 test sequence passing through a 30\\\" channel (15dB of loss at 5.5GHz).\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342747\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
摘要
采用标准数字65nm块体CMOS工艺实现的2抽头DFE接收器，针对低功耗和面积进行了积极优化。通过采用半速率架构、采样前端、软判决直接反馈均衡和轨对轨CMOS时钟，实现了接收机0.22 mW/Gbps的功率/速度比和30 μ m × 40 μ m的核心区。在11gb /s (0.9V供电2.6mA)下，当PRBS7测试序列通过30”通道(5.5GHz时损耗为15dB)时，误码率小于10-14。
An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS
A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10-14 with a PRBS7 test sequence passing through a 30" channel (15dB of loss at 5.5GHz).
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