{"title":"A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning","authors":"Keng-Jan Hsiao, Tai-Cheng Lee","doi":"10.1109/VLSIC.2007.4342730","DOIUrl":null,"url":null,"abstract":"A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.