{"title":"A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue","authors":"Minjae Lee, A. Abidi","doi":"10.1109/VLSIC.2007.4342701","DOIUrl":null,"url":null,"abstract":"A 9 b 1.25 ps two step time-to-digital converter is implemented in 90 nm CMOS. It uses a new circuit to amplify the time residue, and compensates mismatch with subrange normalization. DNL and INL are, respectively, plusmn0.8 LSB and plusmn2 LSB. It can be used as a phase detector with digital output.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"144 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"120","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 120
Abstract
A 9 b 1.25 ps two step time-to-digital converter is implemented in 90 nm CMOS. It uses a new circuit to amplify the time residue, and compensates mismatch with subrange normalization. DNL and INL are, respectively, plusmn0.8 LSB and plusmn2 LSB. It can be used as a phase detector with digital output.