{"title":"一个0.5V 8bit 10Msps的90纳米CMOS流水线ADC","authors":"Junhua Shen, P. Kinget","doi":"10.1109/VLSIC.2007.4342715","DOIUrl":null,"url":null,"abstract":"A true low voltage 0.5 V 8 bit pipelined A/D converter is realized in 90 nm CMOS technology using regular Vtau devices. A cascaded sampling technique is used to combat the OFF leakage of the switches. The converter prototype occupies 0.85 mm2; operating at 10 Msps, it consumes 2.4 mW and achieves an SNDR of 48.1 dB with a 0.4 Vppdiff full-scale input.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS\",\"authors\":\"Junhua Shen, P. Kinget\",\"doi\":\"10.1109/VLSIC.2007.4342715\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A true low voltage 0.5 V 8 bit pipelined A/D converter is realized in 90 nm CMOS technology using regular Vtau devices. A cascaded sampling technique is used to combat the OFF leakage of the switches. The converter prototype occupies 0.85 mm2; operating at 10 Msps, it consumes 2.4 mW and achieves an SNDR of 48.1 dB with a 0.4 Vppdiff full-scale input.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342715\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
采用常规Vtau器件,在90 nm CMOS工艺下实现了一个真正的低电压0.5 V 8位流水线A/D转换器。采用级联采样技术来防止开关泄漏。转换器原型占地0.85 mm2;工作频率为10 Msps,功耗为2.4 mW,在0.4 Vppdiff满量程输入下实现48.1 dB的SNDR。
A true low voltage 0.5 V 8 bit pipelined A/D converter is realized in 90 nm CMOS technology using regular Vtau devices. A cascaded sampling technique is used to combat the OFF leakage of the switches. The converter prototype occupies 0.85 mm2; operating at 10 Msps, it consumes 2.4 mW and achieves an SNDR of 48.1 dB with a 0.4 Vppdiff full-scale input.