采用8平方的非对称保险丝和90nm CMOS的核心器件，设计了一种具有15μm2单元的512×8电保险丝存储器

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342771

Shine C. Chung, Jiann-Tseng Huang, P. Chen, F. Hsueh

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引用次数: 3

摘要

设计了一个15 μm2单元4kb的电保险丝存储器，采用90 nm CMOS芯片，仅使用核心器件。N+ 8平方的非对称引信用于增强引信的均匀性、可靠性和聚合电迁移。高增益级联放大器感测小电阻差异，在1 μ s内实现2.25 V程序电压。一个充分的设计窗口是推导和验证使用片上电阻监视器没有面积开销。

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A 512×8 electrical fuse memory with 15μm2 cells using 8-sq asymmetric fuse and core devices in 90nm CMOS

A 15 μm2 cell 4 Kb electrical fuse memory is designed in 90 nm CMOS using core devices only. The N+ 8-sq asymmetric fuses are used to enhance fuse uniformity, reliability, and aggregate electro-migration. High-gain cascade amplifiers sense small resistance differences to achieve a 2.25 V program voltage in 1 mus. A sufficient design window is derived and verified by using on-chip resistance monitor without area overheads.

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2007 IEEE Symposium on VLSI Circuits

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