一个完全集成的36MHz到230MHz乘法DLL与自适应电流调谐

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342730

Keng-Jan Hsiao, Tai-Cheng Lee

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引用次数: 3

摘要

一种基于乘式dll的频率合成器，具有完全集成的环路电容，采用自适应电流调节环路，为LCD面板应用产生低抖动时钟。测量的RMS抖动为3.5 ps的229.5 mhz输出时钟。频率合成器在0.18 mum CMOS技术中占用0.09 mm2有源面积，从1.8 v电源消耗9 mW。

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A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning

A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.

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2007 IEEE Symposium on VLSI Circuits

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