Solid-state Electronics最新文献

{"title":"Study of RRAM devices with PECVD silicon-oxide resistive switching layer","authors":"Ivan Lisovyi ,&nbsp;Bartłomiej Stonio ,&nbsp;Jakub Jasiński ,&nbsp;Piotr Wiśniewski","doi":"10.1016/j.sse.2025.109208","DOIUrl":"10.1016/j.sse.2025.109208","url":null,"abstract":"<div><div>In this work, we study the RRAM devices with PECVD silicon-oxide layer in a Al(Ni)/SiO_x/Cr structure. We perform the electrical characterization, analyze the extracted parameters in HRS and LRS states. Statistical distribution of the extracted parameters were also presented and analyzed. Transport mechanisms for different voltage range and device states were identified. Low-temperature process used to fabricate the presented devices is advantageous due to the possibility of BEOL integration.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109208"},"PeriodicalIF":1.4,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration of W vias for individual coupling control in 28 nm FD-SOI qubit arrays","authors":"G.A. Elbaz ,&nbsp;J. Pelloux-Prayer ,&nbsp;K. Gruel ,&nbsp;P. Torresani ,&nbsp;R. Lethiecq ,&nbsp;P.L. Julliard ,&nbsp;C. Suarez-Segovia ,&nbsp;F. Arnaud ,&nbsp;E. Nowak ,&nbsp;T. Meunier ,&nbsp;B.C. Paz","doi":"10.1016/j.sse.2025.109205","DOIUrl":"10.1016/j.sse.2025.109205","url":null,"abstract":"<div><div>Using known industrial fabrication methods, we repurpose W vias and, with a single contact patterning step, integrate both gates to define the electrochemical potential of quantum dots (QDs) and vias to define their coupling barriers in CMOS-based, linear qubit arrays. We show both simulated and experimental results of individual coupling control of QDs in arrays that were fully fabricated in a foundry on the 28 nm FD-SOI platform. We show detailed wafer-level transfer characteristics for each barrier implemented on a 1x3 linear array, at room temperature and at 2 K, which demonstrate that the vias are well-behaved MOSFET gates with electrostatic control over the Si channel.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109205"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144879307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental investigation of 7-level stacked nanosheet nMOSFETs for high-temperature applications","authors":"Michelly de Souza ,&nbsp;Marcelo A. Pavanello ,&nbsp;Mikaël Cassé ,&nbsp;Sylvain Barraud","doi":"10.1016/j.sse.2025.109207","DOIUrl":"10.1016/j.sse.2025.109207","url":null,"abstract":"<div><div>This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109207"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144885395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature influence on analog parameters of vertical nanowire transistors","authors":"V.C.P. Silva ,&nbsp;A.R. Ribeiro ,&nbsp;J.A. Martino ,&nbsp;A. Veloso ,&nbsp;N. Horiguchi ,&nbsp;P.G.D. Agopian","doi":"10.1016/j.sse.2025.109206","DOIUrl":"10.1016/j.sse.2025.109206","url":null,"abstract":"<div><div>This study investigates the impact of high temperatures on DC analog parameters of vertical nanowire pMOSFET (V-pFET). Measurements were performed at three temperatures (25 °C, 100 °C and 150 °C), where the main electrical parameters were analyzed. The results indicated an unexpected increase in the drain current and transconductance (gm) over the entire gate voltage range as temperature increased. This behavior is attributed to the competition of different effects such as the strong threshold voltage reduction and mobility degradation caused by the vertical electric field and the influence of high access resistance, which modifies the potential drop across the channel and alters the electric field distribution. On the other hand, the subthreshold slope (SS) exhibited the expected temperature dependence. However, when the temperature increases, the output conductance showed a slight variation. The Early voltage (V_EA) increased with temperature, indicating a reduction in the Early effect. Despite this variation, the intrinsic voltage gain remained remarkably stable when expressed in decibels—approximately 34–36 dB for the device with 400 nanowires—demonstrating good thermal robustness of analog performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109206"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Negative capacitance and negative dielectric behavior of MIS device with Rhenium-Type Schottky contacts","authors":"Mehmet İzzeddin Güler ,&nbsp;Ahmet Kaymaz ,&nbsp;Esra Evcin-Baydilli ,&nbsp;Haziret Durmuş ,&nbsp;Şemsettin Altındal","doi":"10.1016/j.sse.2025.109204","DOIUrl":"10.1016/j.sse.2025.109204","url":null,"abstract":"<div><div>This study offers a thorough examination of the negative capacitance/dielectric behavior of an MIS device with rhenium (Re) type Schottky contact and native oxide interlayer. The pulsed laser deposition method was used to deposit Re as the Schottky contact on the n-type GaAs substrates. Thus, the electrical and dielectric properties were evaluated by <em>I-V, C-V,</em> and <em>G/ω-V</em> tests at<!--> <!-->a high frequency (1 MHz). Experimental results demonstrated that capacitance characteristics showed a marked increase from the inversion region to depletion, with a localized peak observed at 0.26 V. Exceeding 4.16 V, the capacitance values turn negative, signifying a shift to inductive behavior, as shown by a rapid increase in conductance values under the same conditions. In addition, the dynamic resistance profile indicates that the series resistance (<em>R_s</em>) reaches its peak at near-zero bias and stabilizes under significant forward bias, approaching the device’s intrinsic series resistance. Analysis of the <em>C–G/ω–V</em> data also showed two distinct peaks in the corrected conductance (<em>Gc/ω</em>) at –0.55  V and + 0.1  V, due to the response of interface states (<em>N_ss</em>) located at distinct energy levels inside the GaAs bandgap. The transition from capacitive to inductive behavior was recorded with high enough forward bias, at which point the dielectric constant (<em>ε′</em>) turns negative, showing the effects of polarization reversal and reactive energy storage. Additionally, the complex impedance analysis revealed distorted semicircular arcs and loop formations, indicative of interfacial inhomogeneities and multiple charge transport channels. As a result, these findings demonstrate that integrating Re into the MIS structure significantly improves the device’s electrical stability and functional response under varying bias conditions, demonstrating its potential in advanced high-frequency and low-power electronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109204"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct extraction of parasitic source and drain resistances in MOSFETs using saturation current ratio","authors":"Ji Won Park ,&nbsp;Seonghyeon Jeong ,&nbsp;Hanbin Lee ,&nbsp;So-Jeong Park ,&nbsp;Jeong Yeon Im ,&nbsp;Dae Hwan Kim ,&nbsp;Yoon Jung Lee ,&nbsp;Dong Myong Kim ,&nbsp;Sung-Jin Choi","doi":"10.1016/j.sse.2025.109209","DOIUrl":"10.1016/j.sse.2025.109209","url":null,"abstract":"<div><div>We propose a saturation current ratio technique (SCRT) for the separate extraction of parasitic source and drain resistances (<em>R_S</em> and <em>R_D</em>) in metal–oxide–semiconductor field-effect transistors (MOSFETs). Unlike conventional methods that require multiple devices or prior knowledge of device parameters, SCRT enables accurate characterization of parasitic resistances using a single device through simple DC measurements. The technique employs a dual configuration by alternating the roles of the source and drain during forward and reverse measurement sweeps. By analyzing the ratio between the drain saturation currents measured in each configuration, SCRT effectively separates <em>R_S</em> and <em>R_D</em> by quantifying their individual contributions to the voltage drop across the source and drain terminals. Experimental validation on both n-channel and p-channel MOSFETs with various channel lengths and widths confirms the robustness, accuracy, and reproducibility of the proposed method. SCRT offers a practical and efficient approach for characterizing asymmetric parasitic resistances in individual devices, making it a reliable alternative to conventional extraction techniques.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109209"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144840762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantitative analysis on z-interference using reprogram scheme in 3D NAND flash memory Vth distribution","authors":"Jooyoung Lee ,&nbsp;Jinil Yoo ,&nbsp;Hyungcheol Shin","doi":"10.1016/j.sse.2025.109198","DOIUrl":"10.1016/j.sse.2025.109198","url":null,"abstract":"<div><div>In this research, we investigated the impact of Reprogram scheme on Z-interference mitigation in the threshold voltage (V_th) distribution of 3D NAND Flash Memory. Statistical Monte-Carlo Simulation was conducted to reproduce the distribution arising from multiple cells, and Incremental Step Pulse Programming (ISPP) was used. During this process, Random Telegraph Noise (RTN) and ISPP noise were applied. The results enabled us to observe the changes in the distribution reflecting reduced z-interference, which were analyzed from various perspectives. It was confirmed that the distribution width, standard deviation of read level intervals, and number of outlier cells are all decreased. Furthermore, we examined the influence of z-interference according to distribution window settings and the application of reprogram scheme.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109198"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source/drain metal-dependent oxygen scavenging from the viewpoint of the decoupling between source/drain resistance and threshold voltage in InGaZnO thin-film transistors","authors":"Seungki Kim ,&nbsp;Wonjung Kim ,&nbsp;Seong Hoon Jeon ,&nbsp;Changwook Kim ,&nbsp;Dong Myong Kim ,&nbsp;Sung-Jin Choi ,&nbsp;Yoon Jung Lee ,&nbsp;Dae Hwan Kim","doi":"10.1016/j.sse.2025.109202","DOIUrl":"10.1016/j.sse.2025.109202","url":null,"abstract":"<div><div>Reducing source-drain resistance (R_SD) in oxide semiconductor thin-film transistors (TFTs) mainly impacts the performance and reliability of devices and circuits. Oxygen scavenging (OS) is commonly used during process integration to reduce R_SD, including contact resistance between source-drain (S/D) metal and oxide semiconductors. Meanwhile, the lower R_SD, the better, but the threshold voltage (V_T) should be optimized depending on the application. Therefore, it is essential to decouple R_SD and V_T when applying OS.</div><div>In this study, the OS effect depending on the S/D metal of amorphous InGaZnO (a-IGZO) TFT was investigated from the perspective of decoupling R_SD and V_T. As a result of comparing Cu, Ti, and Al as S/D metals, when Al, which has a high metal–oxygen (M−O) bond strength, was used as the source-drain metal, V_T and R_SD decreased and on-current (I_on) increased compared to when Ti was used. A comprehensive analysis of TFT’s electrical characteristics (V_T, mobility, I_on), X-ray photoelectron spectroscopy (XPS), subgap density of states (DoS), and lateral distribution of thermal equilibrium carrier concentration (n₀(y)) indicates that the occurrence and diffusion of oxygen vacancy (V_O) due to OS in the S/D region cause an increase in subgap DoS and gate-to-S/D overlap length (L_OV) and a decrease in V_T due to an increase in donor concentration in the center of the channel (N_CH) due to a change in n₀(y) profile.</div><div>While R_SD changes before and after post-annealing are ×1.087 (Cu), ×0.606 (Ti), and ×0.283 (Al), N_CH changes are ×0.985 (Cu), ×1.267 (Al), and ×1.183 (Ti). The ΔV_T’s before and after post-annealing are + 0.119 V (Cu), −0.206 V (Al), and − 0.045 V (Ti), while ΔI_on’s are ×0.724 (Cu), ×1.222 (Al), and ×1.193 (Ti). Therefore, it is found that Ti is more advantageous than Al in terms of decoupling R_SD and V_T.</div><div>Our result becomes more critical in employing oxide semiconductor TFTs as the back end of line (BEOL) devices because the phenomenon of V_T being affected in improving R_SD using OS can become more severe in high-temperature processes. Furthermore, our result suggests that when selecting S/D metals and annealing conditions for OS, it is necessary to fully consider not only the R_SD reduction but also the degree to which R_SD and V_T can be decoupled.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109202"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144779380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of operation delay and switching speed limitation due to source/drain resistance and subgap density of states in amorphous InGaZnOx/HfZrOx ferroelectric thin-film transistor","authors":"Sejun Park ,&nbsp;Hyojin Yang ,&nbsp;Haesung Kim ,&nbsp;Hyunwook Jeong ,&nbsp;Sung-Jin Choi ,&nbsp;Dae Hwan Kim ,&nbsp;Dong Myong Kim ,&nbsp;Min-Kyu Park ,&nbsp;Jong-Ho Bae","doi":"10.1016/j.sse.2025.109203","DOIUrl":"10.1016/j.sse.2025.109203","url":null,"abstract":"<div><div>In recent years, ferroelectric memory has garnered significant attention as a next-generation non-volatile memory capable of operating at a low voltage and high speed, making it suitable for embedded memory and in-memory computing applications. Previous research has extensively focused on optimizing the polarization switching speed and operational characteristics of ferroelectric thin films themselves. Recent studies have also demonstrated experimental implementations of memory devices utilizing various semiconductors beyond silicon channels. However, to effectively apply and evaluate ferroelectrics at the transistor level for memory applications, it is crucial to consider not only the intrinsic properties of ferroelectric materials but also to integrate and analyze the performance characteristics of transistors. The size of ferroelectric field effect transistors (FeFET) and the characteristics of semiconductor channel material can significantly influence memory performance and operational speed. Differences in performance may arise depending on the semiconductor channel employed and how defects respond within the materials other than ferroelectric film.</div><div>In this study, ferroelectric thin-film transistors (FeTFTs) and corresponding test element group (TEG) with an amorphous InGaZnO_x (a-IGZO) channel and HfZrO_x (HZO) ferroelectric insulator were fabricated and analyzed to investigate the correlation between operational speed and semiconductor channel properties. Measurements, including DC transfer curves, gate capacitance versus gate voltage (<em>C</em>_GDS–<em>V</em>_G) curves, and the frequency dispersion of <em>C</em>_GDS, were conducted. The results confirmed potential limitations in operational speed due to a-IGZO channel characteristics. TCAD simulations were calibrated considering the extracted subgap density of states (DOS) and contact serial resistance, revealing that the speed of FeTFTs can be constrained by serial resistance and defect responses. These findings underscore the necessity of selecting appropriate device structures and materials for effectively evaluating FeTFTs, and highlight the complexities involved in assessing ferroelectric memory performance, emphasizing the interplay between ferroelectric films and semiconductor channels, interface charges, defect levels influenced by processes, and inherent semiconductor channel performance. This research provides insights into the comprehensive analysis required for evaluating ferroelectric memory devices effectively.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109203"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144809638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Small signal PD SOI MOSFET model: considering impact ionization and self-heating effects","authors":"Narendra Pratap Singh ,&nbsp;Shashank Banchhor ,&nbsp;Ashutosh Yadav ,&nbsp;Ashwaini Goswami ,&nbsp;Avinash Singh ,&nbsp;Rohit Ranjan ,&nbsp;Sudeb Dasgupta ,&nbsp;Anand Bulusu","doi":"10.1016/j.sse.2025.109200","DOIUrl":"10.1016/j.sse.2025.109200","url":null,"abstract":"<div><div>The floating body (FB) effect in Partially Depleted (PD) Silicon-on-Insulator (SOI) devices has the potential to be utilized for enhancing energy efficiency. This is because the floating body potential can be leveraged to modulate the threshold voltage, thereby improving headroom in analog circuit design and thus enabling low-voltage operation. We propose a novel physics-based FB potential model that considers impact ionization (II) and self-heating (SH) effects for low terminal bias (V_DS and V_GS​) operation. Subsequently, the proposed FB potential model is utilized to develop a model for the small-signal parameters (gm and Ro​) of a PD SOI device. This proposed model will be useful for an analog designers to design an energy-efficient analog circuits by considering hitherto unused FB effects in mature PDSOI technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109200"},"PeriodicalIF":1.4,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}