Solid-state Electronics最新文献_第5页

TLM-based numerical extraction for CMOS-compatible N+-InGaAs ohmic contacts on 200mm Si substrates 基于tlm的200mm Si衬底上cmos兼容N+-InGaAs欧姆触点的数值提取

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-01 DOI: 10.1016/j.sse.2025.109112

A. Lombrez , A. Divay , H. Boutry , L. Colas , N. Coudurier , S. Altazin , T. Baron

引用次数: 0

Substrate crosstalk characterization for optimized isolation in FDSOI FDSOI中优化隔离的衬底串扰特性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-31 DOI: 10.1016/j.sse.2025.109117

Talha Chohan , Zhixing Zhao , Luca Pirro , Loren Dombroske , Jacob Ong , Olaf Zimmerhackl , Steffen Lehmann , David Pritchard , Tao Xue , Jan Hoentschel

{"title":"Substrate crosstalk characterization for optimized isolation in FDSOI","authors":"Talha Chohan , Zhixing Zhao , Luca Pirro , Loren Dombroske , Jacob Ong , Olaf Zimmerhackl , Steffen Lehmann , David Pritchard , Tao Xue , Jan Hoentschel","doi":"10.1016/j.sse.2025.109117","DOIUrl":"10.1016/j.sse.2025.109117","url":null,"abstract":"<div><div>The coupling (crosstalk) between devices through substrate is a limiting factor for the highly integrated mixed-mode and high frequency circuits. Silicon–On–Insulator(SOI) wafer with buried oxide (BOX) inherits better low frequency isolation compared to bulk silicon. However, at higher frequencies the advantage subsides due to capacitive coupling. For the mixed mode applications, the abrupt signal switching in digital circuitry poses a detrimental effect on the noise-sensitive analog circuitry. This work studies the crosstalk isolation in commercial SOI resistivity substrate (∼1–100 Ω.cm) by deploying design-based approaches for crosstalk reduction. A clear advantage of SOI vs standard bulk is reported especially for low-frequency range. Substrate well variance with different types of junctions is studied and demonstrated to reduce noise isolation. Moreover, a novel guard-ring scheme deploying the combination of resistive and capacitive elements has shown to have improvement in the noise isolation for wide band applications compared to the individual elements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109117"},"PeriodicalIF":1.4,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of electron mobility in 7-level stacked nanosheet GAA nMOSFETs 7能级堆叠纳米片GAA nmosfet中电子迁移率分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-28 DOI: 10.1016/j.sse.2025.109115

Michelly de Souza , Jaime Calçade Rodrigues , Lucas Mota Barbosa da Silva , Flavio Enrico Bergamaschi , Mikaël Cassé , Sylvain Barraud , Olivier Faynot , Marcelo Antonio Pavanello

{"title":"Analysis of electron mobility in 7-level stacked nanosheet GAA nMOSFETs","authors":"Michelly de Souza , Jaime Calçade Rodrigues , Lucas Mota Barbosa da Silva , Flavio Enrico Bergamaschi , Mikaël Cassé , Sylvain Barraud , Olivier Faynot , Marcelo Antonio Pavanello","doi":"10.1016/j.sse.2025.109115","DOIUrl":"10.1016/j.sse.2025.109115","url":null,"abstract":"<div><div>In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109115"},"PeriodicalIF":1.4,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143785792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions 纳米级双栅无结晶体管的解析建模，包括源极和漏极下搭区影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-25 DOI: 10.1016/j.sse.2025.109105

Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis

{"title":"Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions","authors":"Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis","doi":"10.1016/j.sse.2025.109105","DOIUrl":"10.1016/j.sse.2025.109105","url":null,"abstract":"<div><div>In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109105"},"PeriodicalIF":1.4,"publicationDate":"2025-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143725758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent progress in bipolar and heterojunction bipolar transistors on SOI SOI上双极和异质结双极晶体管的研究进展

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-20 DOI: 10.1016/j.sse.2025.109101

Soumya Ranjan Panda , Thomas Zimmer , Anjan Chakravorty , Sebastien Fregonese

引用次数: 0

Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions 扩大Zn0.15Sn0.85(Se0.95S0.05)2晶体在近红外光电子学、传感和范德华异质结中的应用潜力

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-15 DOI: 10.1016/j.sse.2025.109104

Yash N. Doshi , Dixita S. Parmar , Ajay D. Zanpadiya , Aditi P. Pathak , Divya R. Solanki , Dimple V. Shah , Vishva M. Jain , Hiren N. Desai , Piyush B. Patel

{"title":"Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions","authors":"Yash N. Doshi , Dixita S. Parmar , Ajay D. Zanpadiya , Aditi P. Pathak , Divya R. Solanki , Dimple V. Shah , Vishva M. Jain , Hiren N. Desai , Piyush B. Patel","doi":"10.1016/j.sse.2025.109104","DOIUrl":"10.1016/j.sse.2025.109104","url":null,"abstract":"<div><div>Layered Zn<sub>0.15</sub>Sn<sub>0.85</sub>(Se<sub>0.95</sub>S<sub>0.05</sub>)<sub>2</sub> (Q2) crystals with a hexagonal crystalline structure were grown using the direct vapor transport technique (DVT). This research explores applications of the grown Q2 crystals as a near-infrared (NIR) photodetector, vacuum pressure sensor, and Van der Waals heterojunction. The NIR photodetector demonstrating stable, rapid switching with an improved responsivity of 153.38 mAW<sup>-1</sup>. A Q2 crystal-based NIR photodetector achieves an external quantum efficiency of 21.17 %. The Maxwellian distribution was applied to analysis trap depth of NIR photodetector. Additionally, the pulse resistive response of the Q2 crystal-based vacuum pressure sensor was evaluated across a vacuum pressure range from −1033 mbar to 0 mbar. The sensor exhibited a stable response, with 61.27 % at −1033 mbar and 5.85 % at −133 mbar with an average delay time of 2.99 s. Furthermore, the Van der Waals heterojunction device formed by the grown p-type Q2 crystals with another n-type quaternary crystal was studied using the thermionic-emission (TE) model. The ideality factors have been defined in the range of 1 to 2 by studying the current voltage (I-V) characteristics under different temperatures.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109104"},"PeriodicalIF":1.4,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143642555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Intense near-infrared electroluminescence properties from ZnO:Yb LED ZnO:Yb LED的强近红外电致发光特性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-12 DOI: 10.1016/j.sse.2025.109102

Qingxue Zhao , Shenwei Wang , Zhengmao Wen , Weifang Zhang , Xiaoxia Duan , Lixin Yi

引用次数: 0

Traps characterization in RF SOI substrates including a buried SiGe layer 射频 SOI 基底（包括埋入的 SiGe 层）中的陷波表征

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-11 DOI: 10.1016/j.sse.2025.109103

Y. Yan , M. Rack , M. Vanbrabant , M. Nabet , A. Goebel , P. Clifton , J.-P. Raskin

引用次数: 0

An efficient temperature dependent compact model for nanosheet FET for neuromorphic computing circuit 用于神经形态计算电路的纳米片场效应晶体管的高效温度相关紧凑模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-10 DOI: 10.1016/j.sse.2025.109096

N. Aruna Kumari , Abhishek Kumar Upadhyay , Vikas Vijayvargiya , Gaurav Singh , Ankur Beohar , Prithvi P.

引用次数: 0

Low power consumption of non-volatile memory device by tunneling process engineering 隧道工艺设计的低功耗非易失性存储器

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-03-09 DOI: 10.1016/j.sse.2025.109100

Fucheng Wang , Mengmeng Chu , Jingwen Chen , Zhong Pan , Yongsang Kim , Jang kun Song , Muhammad Quddamah Khokhar , Junsin Yi

{"title":"Low power consumption of non-volatile memory device by tunneling process engineering","authors":"Fucheng Wang , Mengmeng Chu , Jingwen Chen , Zhong Pan , Yongsang Kim , Jang kun Song , Muhammad Quddamah Khokhar , Junsin Yi","doi":"10.1016/j.sse.2025.109100","DOIUrl":"10.1016/j.sse.2025.109100","url":null,"abstract":"<div><div>Compared with Si<sub>3</sub>N<sub>4</sub> and Al<sub>2</sub>O<sub>3</sub>, SiO<sub>2</sub> grown using thermal oxidation process as tunneling layer has the advantages of high bandgap and well interface contact with the surface of silicon wafer, which can be a great solution to the leakage current problem of metal–insulator-semiconductor (MIS) devices. This study investigates the effect of improving the SiO<sub>2</sub> tunnel layer on the operating voltage of MIS devices with a SiO<sub>2</sub>/HfAlO<sub>x</sub>/Al<sub>2</sub>O<sub>3</sub> structure. The result shows the operating voltage changes as the tunneling layer thickness decreases, with a minimum of only 12 V for a 1.5 nm tunneling layer thickness. In addition, we found that pinholes are generated on the film surface when annealing a 1.5 nm SiO<sub>2</sub> tunnel layer at 850 °C N<sub>2</sub>, in which case the operating voltage of the device is reduced to only 10 V, though it was also accompanied by the deterioration of the retention characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109100"},"PeriodicalIF":1.4,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143627960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0