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C-V characterization of the trap-rich layer in a novel Double-BOX structure 新型双 BOX 结构中陷阱丰富层的 C-V 特性分析
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-05-09 DOI: 10.1016/j.sse.2024.108951
Yang Huang , Fanyu Liu , Sorin Cristoloveanu , Shiqi Ma , Massinissa Nabet , Yiyi Yan , Bo Li , Binhong Li , Bich-Yen Nguyen , Zhengsheng Han , Jean-Pierre Raskin
{"title":"C-V characterization of the trap-rich layer in a novel Double-BOX structure","authors":"Yang Huang ,&nbsp;Fanyu Liu ,&nbsp;Sorin Cristoloveanu ,&nbsp;Shiqi Ma ,&nbsp;Massinissa Nabet ,&nbsp;Yiyi Yan ,&nbsp;Bo Li ,&nbsp;Binhong Li ,&nbsp;Bich-Yen Nguyen ,&nbsp;Zhengsheng Han ,&nbsp;Jean-Pierre Raskin","doi":"10.1016/j.sse.2024.108951","DOIUrl":"10.1016/j.sse.2024.108951","url":null,"abstract":"<div><p>A new Double-BOX structure is introduced to explore the electrical properties of the trap-rich layer used to enhance the performance of radio frequency Silicon-on-Insulator substrates. Capacitance-voltage (C-V) measurements reveal anomalous behavior with a “shoulder” emerging in the electron accumulation region and a shift towards negative gate voltage in hysteresis. TCAD simulation shows that these features are related to trap states at the grain boundary in the trap-rich polycrystalline silicon (polysilicon) layer. These traps form a potential barrier and affect the C-V curves. To determine the traps density in polysilicon, a three-element circuit model is used. The effective density of fast traps is evaluated from the corrected C-V curve, while the hysteresis of double-sweep C-V measurement yields the slow traps density at the grain boundary in polysilicon.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108951"},"PeriodicalIF":1.7,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141025738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Detailed analysis of the capacitance characteristic measured using the pseudo-metal–oxide–semiconductor method 使用伪金属氧化物半导体法测量电容特性的详细分析
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-05-06 DOI: 10.1016/j.sse.2024.108950
Shingo Sato , Yifan Yuan
{"title":"Detailed analysis of the capacitance characteristic measured using the pseudo-metal–oxide–semiconductor method","authors":"Shingo Sato ,&nbsp;Yifan Yuan","doi":"10.1016/j.sse.2024.108950","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108950","url":null,"abstract":"<div><p>This paper discusses the capacitance–voltage (C–V) characteristics of a silicon-on-insulator (SOI) wafer obtained using the alternating current (AC) pseudo-metal–oxide–semiconductor (MOS) method. This study clarified that the C–V characteristics measured using the standard configuration of the AC pseudo-MOS method were strongly ruled by the condition of both the top and back contacts. Using a distinctive setup referred to as the Kelvin AC pseudo-MOS method, coupled with specific treatments applied to the wafer, we acquired C–V and impedance-related characteristics that differed from the standard configuration and aligned with the theoretical expectation for the entire range of measurement frequencies below a few megahertz. In addition, this study demonstrated the qualitative behavior of the frequency-dependent capacitance with the channel conduction of carriers using an analytical model.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108950"},"PeriodicalIF":1.7,"publicationDate":"2024-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140879504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stable and repeatable ZrO2 RRAM achieved by NiO barrier layer for negative set phenomenon elimination 通过氮氧化物阻挡层消除负集现象，实现稳定且可重复的 ZrO2 RRAM
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-05-03 DOI: 10.1016/j.sse.2024.108948
Tangyou Sun , Fantao Yu , Chengcheng Li , Taohua Ning , Xingpeng Liu , Zhimou Xu , Zhiqiang Yu , Chunsheng Jiang , Haiou Li , Fabi Zhang , Qing Liao
{"title":"Stable and repeatable ZrO2 RRAM achieved by NiO barrier layer for negative set phenomenon elimination","authors":"Tangyou Sun ,&nbsp;Fantao Yu ,&nbsp;Chengcheng Li ,&nbsp;Taohua Ning ,&nbsp;Xingpeng Liu ,&nbsp;Zhimou Xu ,&nbsp;Zhiqiang Yu ,&nbsp;Chunsheng Jiang ,&nbsp;Haiou Li ,&nbsp;Fabi Zhang ,&nbsp;Qing Liao","doi":"10.1016/j.sse.2024.108948","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108948","url":null,"abstract":"<div><p>Resistive random-access memory (RRAM) is a promising non-volatile memory technology due to its fast operation, low power consumption, and high reliability. However, the negative set phenomenon remains a challenge for RRAM, which can lead to the deterioration of device switching parameters. In this study, we successfully addressed this issue by inserting a NiO blocking layer between the ZrO<sub>2</sub> and Ag top electrodes in ZrO<sub>2</sub>-based RRAM. In addition, the resistive switching characteristics of the device are significantly enhanced by the incorporation of a p-type oxide NiO layer. Compared to single-layer ZrO<sub>2</sub> devices, the double-layer Ag/NiO/ZrO<sub>2</sub>/ITO RRAM exhibits improved cycling durability (&gt;500 cycles) and good retention time (3 × 10<sup>4</sup>s). Our analysis of the device conduction mechanism and proposed resistive switching model suggest that oxygen vacancies play a connecting role in the reset process, leading to failed reset behavior. Through the incorporation of a p-type semiconductor NiO layer into ZrO<sub>2</sub>-based RRAMs, the interference of oxygen vacancies on the reset process can be effectively impeded. This approach not only provides an effective resolution to the unforeseen negative set phenomenon in RRAM devices, but it also holds paramount significance for the advancement of high-performance RRAMs.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108948"},"PeriodicalIF":1.7,"publicationDate":"2024-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140906599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Density functional model of threshold voltage shifts at High-K/Metal gates 高-K/金属栅极阈值电压偏移的密度泛函模型
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-05-03 DOI: 10.1016/j.sse.2024.108949
R. Cao , Z. Zhang , Y. Guo , J. Robertson
{"title":"Density functional model of threshold voltage shifts at High-K/Metal gates","authors":"R. Cao ,&nbsp;Z. Zhang ,&nbsp;Y. Guo ,&nbsp;J. Robertson","doi":"10.1016/j.sse.2024.108949","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108949","url":null,"abstract":"<div><p>A density functional analysis of oxide dipole layers used to set the threshold voltages in high-K/metal CMOS gate stacks is given in terms of the band alignments and chemical trends of these component oxide layers. The oxides SrO, La<sub>2</sub>O<sub>3</sub>, HfO<sub>2</sub> and Al<sub>2</sub>O<sub>3</sub> are found to have similar band gaps and form a ‘staircase’ of band alignments, allowing them to shift the metal electrode Fermi level in both n-type and p-type directions. This analysis supersedes previous largely empirical models based on metal oxide ion densities or electronegativity scales.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108949"},"PeriodicalIF":1.7,"publicationDate":"2024-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140879488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Threshold voltage in FD-SOI MOSFETs FD-SOI MOSFET 的阈值电压
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-30 DOI: 10.1016/j.sse.2024.108947
Georges Pananakakis, Gérard Ghibaudo, Sorin Cristoloveanu
{"title":"Threshold voltage in FD-SOI MOSFETs","authors":"Georges Pananakakis,&nbsp;Gérard Ghibaudo,&nbsp;Sorin Cristoloveanu","doi":"10.1016/j.sse.2024.108947","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108947","url":null,"abstract":"<div><p>The threshold voltage definition and measurement in ultrathin FD-SOI MOS transistors are revisited by comparing theoretical and pragmatic extraction techniques, including novel approaches. The respective merits and limitations of methods based on the monitoring of the potential, mobile charge, gate-to-channel capacitance and drain current are emphasized. Back-gate biasing, thickness-induced quantization, potential fluctuations and surface roughness can enhance the disparity between various extraction methods. The origin of these deviations is clarified.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108947"},"PeriodicalIF":1.7,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141067713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of anomalous C-V behavior for extracting the traps density in the undoped polysilicon with a double-BOX structure 分析反常 C-V 行为以提取双 BOX 结构未掺杂多晶硅中的陷阱密度
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-26 DOI: 10.1016/j.sse.2024.108946
Yang Huang , Yiyi Yan , Massinissa Nabet , Fanyu Liu , Bo Li , Binhong Li , Zhengsheng Han , Sorin Cristoloveanu , Jean-Pierre Raskin
{"title":"Analysis of anomalous C-V behavior for extracting the traps density in the undoped polysilicon with a double-BOX structure","authors":"Yang Huang ,&nbsp;Yiyi Yan ,&nbsp;Massinissa Nabet ,&nbsp;Fanyu Liu ,&nbsp;Bo Li ,&nbsp;Binhong Li ,&nbsp;Zhengsheng Han ,&nbsp;Sorin Cristoloveanu ,&nbsp;Jean-Pierre Raskin","doi":"10.1016/j.sse.2024.108946","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108946","url":null,"abstract":"<div><p>A new Double-BOX structure is introduced to reveal the electrical properties of undoped polysilicon used to enhance the performance of radio frequency SOI substrates. A plateau is clearly observed in the capacitance–voltage (C-V) characteristics, which is due to the influence of the potential barrier formed at the grain boundary. A tangential approximation method based on a three-element circuit model is proposed for correcting the measured C-V curve. With the corrected C-V curve, the effective trap density distribution in polysilicon is determined for each frequency.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108946"},"PeriodicalIF":1.7,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140825123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Forward leakage currents in GaN p-i-n diodes GaN pi-n 二极管的正向漏电流
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-22 DOI: 10.1016/j.sse.2024.108936
Ao Lu , Xiaofei Pan , Xinjie Zhou , Yang Li , Xiao Wang , Jinping Ao , Dawei Yan
{"title":"Forward leakage currents in GaN p-i-n diodes","authors":"Ao Lu ,&nbsp;Xiaofei Pan ,&nbsp;Xinjie Zhou ,&nbsp;Yang Li ,&nbsp;Xiao Wang ,&nbsp;Jinping Ao ,&nbsp;Dawei Yan","doi":"10.1016/j.sse.2024.108936","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108936","url":null,"abstract":"<div><p>Excessive forward leakage currents in GaN p-i-n diodes were investigated. Traditional diffusion mechanism dominates at <em>V</em><sub>F</sub> &gt; 2 V. The effective band gap is derived to be ∼2.21 eV, which is much lower than 3.4 eV and attributed to a band fluctuation caused by dislocations; At 1.35 V &lt; <em>V</em><sub>F</sub> &lt; 2 V, a trap-assisted tunneling process becomes important, whose ideality factor is still larger than 4.1 at <em>T</em> = 400 K; Two distinct power-law relationships were observed at lower biases, separated at <em>V</em><sub>F</sub> = 0.8 V, whose exponents are extracted to be ∼8 and ∼4, respectively. The behavior is in a good agreement with the space-charge-limited model, featuring an exponentially decaying distribution of trap states below the conduction band.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108936"},"PeriodicalIF":1.7,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140647326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Gate Oxide Thickness on Flicker Noise (1/f) in PDSOI n-channel FETs 栅极氧化物厚度对 PDSOI n 沟道场效应晶体管闪烁噪声 (1/f) 的影响
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-16 DOI: 10.1016/j.sse.2024.108935
Shruti Pathak , Sumreti Gupta , Aarti Rathi , P. Srinivasan , Abhisek Dixit
{"title":"Impact of Gate Oxide Thickness on Flicker Noise (1/f) in PDSOI n-channel FETs","authors":"Shruti Pathak ,&nbsp;Sumreti Gupta ,&nbsp;Aarti Rathi ,&nbsp;P. Srinivasan ,&nbsp;Abhisek Dixit","doi":"10.1016/j.sse.2024.108935","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108935","url":null,"abstract":"<div><p>This work reports the impact of gate oxide thickness on flicker noise (1/<em>f</em>) in 45-nm RFSOI NFET devices. In addition, the effect of finger width scaling on 1/<em>f</em> noise parameters is studied in linear region. The dominant source of 1/<em>f</em> noise is also analyzed. It is observed that thin oxide devices show carrier number fluctuation; however, for thick oxide devices, correlated number-mobility govern the noise. Extracted trap densities using 1/<em>f</em> noise show higher volume trap densities in thin oxide devices. Moreover, trap distribution behavior is analyzed using frequency exponent. Further, GLOBALFOUNDRIES PDK is utilized to model 1/<em>f</em> noise behavior of the devices.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108935"},"PeriodicalIF":1.7,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140618841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis of α-Fe2O3 nanorod for sensitive and selective detection of the n-butanol 用于灵敏和选择性检测正丁醇的 α-Fe2O3 纳米棒的合成
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-16 DOI: 10.1016/j.sse.2024.108934
Yina Yang , Yufeng Liu , Xiaohong Zheng , Xinfeng Qiao
{"title":"Synthesis of α-Fe2O3 nanorod for sensitive and selective detection of the n-butanol","authors":"Yina Yang ,&nbsp;Yufeng Liu ,&nbsp;Xiaohong Zheng ,&nbsp;Xinfeng Qiao","doi":"10.1016/j.sse.2024.108934","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108934","url":null,"abstract":"<div><p>In different environments, high concentration of n-butanol will have certain harm to the human senses and nervous system, meanwhile the electrochemical sensor limits its widespread use due to its high power consumption, so it is very meaningful to develop a semiconductor n-butanol sensor with low energy consumption. In this paper, α-Fe<sub>2</sub>O<sub>3</sub> nanorods were prepared by one-step hydrothermal method and then assembled into a n-butanol sensor capable of detecting n-butanol, and the effects of two different calcination temperatures on the performance of the sensor were investigated. Due to its higher Fe<sup>3+</sup> content, higher oxygen vacancy content and larger specific surface area, S1-250 provided more active sites for gas adsorption, which making the response of S1-250 to 100 ppm n-butanol at 215 °C reached to 88.4. Finally, the effect of the calcination temperature on the sensor and the response mechanism were discussed. This paper offers promising applications for low-energy n-butanol sensors assembled from a single material α −Fe<sub>2</sub>O<sub>3</sub>.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108934"},"PeriodicalIF":1.7,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140637989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-performance uniform stepper-based InP double-heterojunction bipolar transistor (DHBT) on a 3-inch InP substrate 基于 3 英寸 InP 基底面的高性能均匀步进式 InP 双兼性双极晶体管 (DHBT)
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-04-16 DOI: 10.1016/j.sse.2024.108933
Seung Heon Shin , Hyeon-Seok Jeong , Yong-Hyun Kim , Yong-Soo Jeon , Ji-Min Beak , Wan-Soo Park , In-Geun Lee , Jacob Yun , Ted Kim , Jae-Hak Lee , Hyuk-Min Kwon , Dae-Hyun Kim
{"title":"High-performance uniform stepper-based InP double-heterojunction bipolar transistor (DHBT) on a 3-inch InP substrate","authors":"Seung Heon Shin ,&nbsp;Hyeon-Seok Jeong ,&nbsp;Yong-Hyun Kim ,&nbsp;Yong-Soo Jeon ,&nbsp;Ji-Min Beak ,&nbsp;Wan-Soo Park ,&nbsp;In-Geun Lee ,&nbsp;Jacob Yun ,&nbsp;Ted Kim ,&nbsp;Jae-Hak Lee ,&nbsp;Hyuk-Min Kwon ,&nbsp;Dae-Hyun Kim","doi":"10.1016/j.sse.2024.108933","DOIUrl":"10.1016/j.sse.2024.108933","url":null,"abstract":"<div><p>In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with <em>W<sub>E</sub></em> = 0.6 μm and <em>L<sub>E</sub></em> = 15 μm exhibits current gain (<em>β</em>) = 50 at <em>V<sub>CE</sub></em> = 1.0 V and an open-base common-emitter breakdown voltage (<em>BV<sub>CEO</sub></em>) of 5.7 V at <em>J<sub>C</sub></em> = 0.01 mA/µm<sup>2</sup> and 7.5 V at <em>J<sub>C</sub></em> = 0.1 mA/µm<sup>2</sup>, respectively. Moreover, the fabricated DHBTs with <em>W<sub>E</sub></em> = 0.6 μm and <em>L<sub>E</sub></em> = 15 μm show excellent <em>f<sub>T</sub></em> of 244 GHz and <em>f<sub>max</sub></em> of 221 GHz at <em>J<sub>C</sub></em> = 4.4 mA/μm<sup>2</sup> and <em>V<sub>CE</sub></em> = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (<em>β</em>) and high-frequency characteristics with <em>W<sub>E</sub></em> = 0.6 μm and <em>L<sub>E</sub></em> = 15 μm and the average values and standard deviation of <em>the β, f<sub>T</sub></em>, and <em>f<sub>max</sub> are β</em> = 49.3 ± 1.9, <em>f<sub>T</sub></em> = 241.4 ± 3.8 GHz, and <em>f<sub>max</sub></em> = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108933"},"PeriodicalIF":1.7,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140781826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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