Solid-state Electronics最新文献_第5页

Multilevel conductance modulation in HfO2, Al2O3, and HfO2/Al2O3 bilayer memristors HfO2， Al2O3和HfO2/Al2O3双层记忆电阻器的多电平电导调制

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-19 DOI: 10.1016/j.sse.2025.109294

H. García , G. Vinuesa , T.del Val , K. Kalam , M.B. González , F. Campabadal , S. Dueñas , H. Castán

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Traps and radio-frequency characterization of polysilicon layer on high resistivity silicon substrate 高电阻率硅衬底上多晶硅层的陷阱和射频特性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-25 DOI: 10.1016/j.sse.2025.109269

Eric Vandermolen , Philippe Ferrandis , Frédéric Allibert , Emmanuel Augendre , Massinissa Nabet , Martin Rack , Jean-Pierre Raskin , Mikaël Cassé

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Band structure-based methodology for analysis of radiation-induced interface traps on reliability of UTB MOS devices 基于波段结构的辐射诱导界面陷阱对UTB MOS器件可靠性分析方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-07 DOI: 10.1016/j.sse.2025.109289

Nalin Vilochan Mishra, Yogesh Dhote, Aditya Sankar Medury

{"title":"Band structure-based methodology for analysis of radiation-induced interface traps on reliability of UTB MOS devices","authors":"Nalin Vilochan Mishra, Yogesh Dhote, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109289","DOIUrl":"10.1016/j.sse.2025.109289","url":null,"abstract":"<div><div>The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (<span><math><mi>α</mi></math></span>, proton, <span><math><mi>γ</mi></math></span>, X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109289"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Pursuing the FD-SOI roadmap down to 10 nm and 7 nm nodes for high energy efficient, low power and RF/mmWave applications 追求FD-SOI路线图至10 nm和7 nm节点，用于高能效，低功耗和RF/毫米波应用

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-11 DOI: 10.1016/j.sse.2025.109264

C. Fenouillet-Beranger, O. Rozeau, R. Chouk, O. Cueto, A-S. Royet, M. Charbonneau, B. Mohamad, L. Brévard, Z. Chalupa, A. Bond, F. Baudin, L. Brunet, P. Rodriguez, R. Gassilloud, T. Mota-Frutuoso, P. Pimenta-Barros, S. Beaurepaire, V. Lapras, J. Kanyandekwe, E. Petitprez, D. Noguet

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Impact of interface traps on the subthreshold performance of InGaAs nanosheet transistors 界面陷阱对InGaAs纳米片晶体管亚阈值性能的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-28 DOI: 10.1016/j.sse.2025.109265

Luigi Balestra , Simone Di Stasi , Elena Gnani , Susanna Reggiani , Mu-Yu Chen , Hiroshi Iwai , Edward Yi Chang

{"title":"Impact of interface traps on the subthreshold performance of InGaAs nanosheet transistors","authors":"Luigi Balestra , Simone Di Stasi , Elena Gnani , Susanna Reggiani , Mu-Yu Chen , Hiroshi Iwai , Edward Yi Chang","doi":"10.1016/j.sse.2025.109265","DOIUrl":"10.1016/j.sse.2025.109265","url":null,"abstract":"<div><div>The performance of InGaAs based transistors can be significantly affected by the presence of interface traps, particularly in the subthreshold regime. In this study, the role of such defects has been investigated through the fabrication and the characterization of MOSCAP structures and nanosheet transistors. TCAD simulations have been used to extract interface-trap densities. Results reveal that the distributed defect tail into the bandgap is <span><math><mo>∼</mo></math></span>5 × 10<sup>11</sup> cm<span><math><mrow><msup><mrow></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup><mspace></mspace><msup><mrow><mi>eV</mi></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msup></mrow></math></span> and degrades the subthreshold slope of about 39%, while interface traps inside the conduction band limit g<span><math><msubsup><mrow></mrow><mrow><mi>m</mi></mrow><mrow><mi>MAX</mi></mrow></msubsup></math></span> to 561 <span><math><mi>μ</mi></math></span>S/<span><math><mi>μ</mi></math></span>m. The study emphasizes the need for improved interface engineering to unlock the full potential of nanoscale InGaAs-based devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109265"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation on dielectric wall variations in Forksheet FETs 叉片场效应管介电壁变化的研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-28 DOI: 10.1016/j.sse.2025.109281

Jae Woog Jung , Jinho Park , Hyunwoo Kim

{"title":"Investigation on dielectric wall variations in Forksheet FETs","authors":"Jae Woog Jung , Jinho Park , Hyunwoo Kim","doi":"10.1016/j.sse.2025.109281","DOIUrl":"10.1016/j.sse.2025.109281","url":null,"abstract":"<div><div>Forksheet FET (FSFET) is a promising candidate to replace the nanosheet FET (NSFET) for sub-3-nm technology nodes, offering further scalability. To realize FSFETs, a dielectric wall (DW) must be positioned between the NMOS and PMOS regions. However, the DW thickness (<em>THK</em><sub>DW</sub>) has a significant influence on the electrical performance of FSFETs, including RC delay and power consumption. In this study, the effects of DW variation on FSFET performance were investigated using 3D TCAD simulations, focusing on RC delay and power characteristics. The DW thickness was varied from 5 nm to 25 nm with respect to the device width, and its influence on NMOS and PMOS characteristics and intrinsic RC delay was analyzed. The performance was further evaluated in terms of RC delay, operating frequency, and power using a CMOS inverter configuration. The results indicate that, at a constant active power, the RC delay continuously improves as <em>THK</em><sub>DW</sub> decreases. However, considering practical DW process limitations, the impact of misalignment during FSFET fabrication was also analyzed. It was found that to retain optimal performance, the misalignment should be restricted to less than 3 nm, ensuring more than 95 % preservation of the original device functionality.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109281"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A mathematical model for non-equilibrium body potential of SOI Pseudo-MOS and physical mechanism analysis SOI伪mos非平衡体势的数学模型及物理机理分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-07 DOI: 10.1016/j.sse.2025.109287

Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye

引用次数: 0

3D simulation of charge defect impact on an industrial 28 nm FD-SOI quantum dot 工业28 nm FD-SOI量子点上电荷缺陷影响的三维模拟

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-29 DOI: 10.1016/j.sse.2025.109285

Benjamin Bureau , Félix Beaudoin , Pericles Philippopoulos , Salvador Mir , Eva Dupont-Ferrier , Philippe Galy

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Nanosheet Transistor Applied in a Two-Stage Operational Transconductance Amplifier from 125 °C down to −100 °C 纳米片晶体管应用于二级操作跨导放大器从125°C到- 100°C

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-05 DOI: 10.1016/j.sse.2025.109291

Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian

{"title":"Nanosheet Transistor Applied in a Two-Stage Operational Transconductance Amplifier from 125 °C down to −100 °C","authors":"Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian","doi":"10.1016/j.sse.2025.109291","DOIUrl":"10.1016/j.sse.2025.109291","url":null,"abstract":"<div><div>This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (g<sub>m</sub> ⁄ I<sub>DS</sub>) of around 8 V<sup>−1</sup> and supply voltage (V<sub>DD</sub>) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (I<sub>SS</sub>) is temperature-compensated (I<sub>SS</sub> and V<sub>CM</sub> are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109291"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Enhanced photoresponse in Cu/n-Si Schottky photodetectors via RF sputtering: A comparative study with thermal evaporation 通过射频溅射增强Cu/n-Si肖特基光电探测器的光响应：与热蒸发的比较研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-01 DOI: 10.1016/j.sse.2025.109268

Rajat Kumar Goyal , Madhuram Mishra , Pragya Kushwaha , Sunil Babu Eadi , Harshit Agarwal

{"title":"Enhanced photoresponse in Cu/n-Si Schottky photodetectors via RF sputtering: A comparative study with thermal evaporation","authors":"Rajat Kumar Goyal , Madhuram Mishra , Pragya Kushwaha , Sunil Babu Eadi , Harshit Agarwal","doi":"10.1016/j.sse.2025.109268","DOIUrl":"10.1016/j.sse.2025.109268","url":null,"abstract":"<div><div>Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109268"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0