Temperature influence on analog parameters of vertical nanowire transistors

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian
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Abstract

This study investigates the impact of high temperatures on DC analog parameters of vertical nanowire pMOSFET (V-pFET). Measurements were performed at three temperatures (25 °C, 100 °C and 150 °C), where the main electrical parameters were analyzed. The results indicated an unexpected increase in the drain current and transconductance (gm) over the entire gate voltage range as temperature increased. This behavior is attributed to the competition of different effects such as the strong threshold voltage reduction and mobility degradation caused by the vertical electric field and the influence of high access resistance, which modifies the potential drop across the channel and alters the electric field distribution. On the other hand, the subthreshold slope (SS) exhibited the expected temperature dependence. However, when the temperature increases, the output conductance showed a slight variation. The Early voltage (VEA) increased with temperature, indicating a reduction in the Early effect. Despite this variation, the intrinsic voltage gain remained remarkably stable when expressed in decibels—approximately 34–36 dB for the device with 400 nanowires—demonstrating good thermal robustness of analog performance.
温度对垂直纳米线晶体管模拟参数的影响
本文研究了高温对垂直纳米线pMOSFET (v - fet)直流模拟参数的影响。在三种温度(25°C, 100°C和150°C)下进行测量,分析主要电气参数。结果表明,随着温度的升高,漏极电流和跨导(gm)在整个栅极电压范围内出乎意料地增加。这种现象是由于垂直电场引起的强阈值电压降低和迁移率下降以及高接入电阻的影响等不同效应的竞争,改变了通道上的电位下降,改变了电场分布。另一方面,阈下斜率(SS)表现出预期的温度依赖性。然而,当温度升高时,输出电导表现出轻微的变化。早期电压(VEA)随温度升高而升高,表明早期效应减弱。尽管存在这种变化,当以分贝表示时,固有电压增益仍然非常稳定——对于带有400纳米线的器件,大约为34-36 dB——表明模拟性能具有良好的热鲁棒性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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