V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian
{"title":"Temperature influence on analog parameters of vertical nanowire transistors","authors":"V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian","doi":"10.1016/j.sse.2025.109206","DOIUrl":null,"url":null,"abstract":"<div><div>This study investigates the impact of high temperatures on DC analog parameters of vertical nanowire pMOSFET (V-pFET). Measurements were performed at three temperatures (25 °C, 100 °C and 150 °C), where the main electrical parameters were analyzed. The results indicated an unexpected increase in the drain current and transconductance (gm) over the entire gate voltage range as temperature increased. This behavior is attributed to the competition of different effects such as the strong threshold voltage reduction and mobility degradation caused by the vertical electric field and the influence of high access resistance, which modifies the potential drop across the channel and alters the electric field distribution. On the other hand, the subthreshold slope (SS) exhibited the expected temperature dependence. However, when the temperature increases, the output conductance showed a slight variation. The Early voltage (V<sub>EA</sub>) increased with temperature, indicating a reduction in the Early effect. Despite this variation, the intrinsic voltage gain remained remarkably stable when expressed in decibels—approximately 34–36 dB for the device with 400 nanowires—demonstrating good thermal robustness of analog performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109206"},"PeriodicalIF":1.4000,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001510","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This study investigates the impact of high temperatures on DC analog parameters of vertical nanowire pMOSFET (V-pFET). Measurements were performed at three temperatures (25 °C, 100 °C and 150 °C), where the main electrical parameters were analyzed. The results indicated an unexpected increase in the drain current and transconductance (gm) over the entire gate voltage range as temperature increased. This behavior is attributed to the competition of different effects such as the strong threshold voltage reduction and mobility degradation caused by the vertical electric field and the influence of high access resistance, which modifies the potential drop across the channel and alters the electric field distribution. On the other hand, the subthreshold slope (SS) exhibited the expected temperature dependence. However, when the temperature increases, the output conductance showed a slight variation. The Early voltage (VEA) increased with temperature, indicating a reduction in the Early effect. Despite this variation, the intrinsic voltage gain remained remarkably stable when expressed in decibels—approximately 34–36 dB for the device with 400 nanowires—demonstrating good thermal robustness of analog performance.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.