Solid-state Electronics最新文献

{"title":"Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM","authors":"Geon Kim ,&nbsp;Jin So ,&nbsp;Eungi Hwang ,&nbsp;Jun Lee ,&nbsp;Garam Kim","doi":"10.1016/j.sse.2025.109258","DOIUrl":"10.1016/j.sse.2025.109258","url":null,"abstract":"<div><div>As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109258"},"PeriodicalIF":1.4,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics","authors":"Najeh Zeidi ,&nbsp;Farès Tounsi ,&nbsp;Jean-Pierre Raskin ,&nbsp;Denis Flandre","doi":"10.1016/j.sse.2025.109261","DOIUrl":"10.1016/j.sse.2025.109261","url":null,"abstract":"<div><div>This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109261"},"PeriodicalIF":1.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of set and reset dynamics on HfO2, Al2O3, and bilayer memristors","authors":"G. Vinuesa ,&nbsp;T. del Val ,&nbsp;K. Kalam ,&nbsp;H. García ,&nbsp;M.B. González ,&nbsp;F. Campabadal ,&nbsp;S. Dueñas ,&nbsp;H. Castán","doi":"10.1016/j.sse.2025.109262","DOIUrl":"10.1016/j.sse.2025.109262","url":null,"abstract":"<div><div>In this study, resistive switching in three structures with HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>, Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>, and bilayer (HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> + Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>) oxides is studied. Electrical characterization reveals differences in switching dynamics and performance across these configurations, highlighting the impact of oxide composition and structure on device behavior. The time needed to reset is defined and studied in detail, showing an exponential dependence with the applied voltage. Finally, an initial assessment of the effect that the set and reset transient has on the multilevel capabilities of the devices is made.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109262"},"PeriodicalIF":1.4,"publicationDate":"2025-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing ultra-thin-barrier AlGaN/GaN HEMTs with LPCVD SiN passivation for high-power applications","authors":"Jui-Sheng Wu ,&nbsp;Chen-Hsi Tsai ,&nbsp;You-Chen Weng ,&nbsp;Edward Yi Chang","doi":"10.1016/j.sse.2025.109260","DOIUrl":"10.1016/j.sse.2025.109260","url":null,"abstract":"<div><div>Ultra-thin-barrier AlGaN/GaN HEMTs offer a gate-recess-free solution but suffer from high on-resistance and current degradation. In this work, ultra-thin-barrier AlGaN/GaN heterostructures with a 1-nm GaN cap and 5-nm Al_0.22Ga_0.78N barrier were fabricated, followed by LPCVD SiN passivation of four different thicknesses (50, 60, 150, and 220 nm) to solve the low carrier density issues associated with thin-barrier structures. The 220 nm LPCVD-SiN passivated device achieves a high <em>I</em>_D,max of 907 mA/mm and the lowest on-resistance of 8.9 Ω·mm. In addition, to evaluate the stability of current output, thinner LPCVD-SiN layers exhibit better current stability under ON-state stress up to 150 °C. These findings highlight the benefits of ultra-thin-barrier AlGaN/GaN HEMTs design for future high-power GaN applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109260"},"PeriodicalIF":1.4,"publicationDate":"2025-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels","authors":"N. Paul ,&nbsp;S. Chattopadhyay","doi":"10.1016/j.sse.2025.109259","DOIUrl":"10.1016/j.sse.2025.109259","url":null,"abstract":"<div><div>The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10⁻⁴ μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10⁻⁷ μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109259"},"PeriodicalIF":1.4,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physics-based compact model of subband energy for GAAFETs including corner rounding and geometric variability analysis utilizing Monte Carlo simulation","authors":"Swapna Sarker,&nbsp;Abhishek Kumar,&nbsp;Avirup Dasgupta","doi":"10.1016/j.sse.2025.109253","DOIUrl":"10.1016/j.sse.2025.109253","url":null,"abstract":"<div><div>We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109253"},"PeriodicalIF":1.4,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Colossal permittivity and defect-engineered conduction in Ag/Al/SiO2/Si/Ag MIS structures for next-generation RRAM and 5G/6G capacitors","authors":"A. Ashery","doi":"10.1016/j.sse.2025.109256","DOIUrl":"10.1016/j.sse.2025.109256","url":null,"abstract":"<div><div>The Ag/Al/SiO₂/Si/Ag metal–insulator-semiconductor (MIS) structure exhibits remarkable dielectric and electrical properties, making it a promising candidate for next-generation electronic applications. This study systematically investigates the colossal permittivity, defect-mediated conduction, and relaxation dynamics of the dual-metal MIS structure using impedance spectroscopy, dielectric analysis, and AC conductivity measurements across wide frequency (1 kHz–20 MHz), temperature (80–400 K), and voltage (±5 V) ranges. Key findings reveal that the Ag/Al electrode configuration induces unique interfacial polarization effects, leading to ultrahigh dielectric constants (ε′ &gt; 103 at low frequencies) and low loss tangents (tanδ &lt; 0.1) suitable for high-frequency capacitors in 5G/6G technologies. The structure also demonstrates voltage-tunable resistive switching via Ag filament formation, enabling ultra-low-power resistive random-access memory (RRAM) with enhanced endurance.</div><div>Novelty: Unlike conventional Al/SiO₂/Si devices, the dual-metal design leverages Ag’s high ionic mobility to modulate defect states and conduction pathways, resulting in: Colossal permittivity from space charge polarization at Ag/SiO₂ and SiO₂/Si interfaces. Defect-engineered conduction via thermally activated hopping and Fowler-Nordheim tunneling. Negative capacitance effects at high frequencies, attributed to charge trapping/detrapping dynamics.</div><div>New Applications:</div><div><strong>RRAM</strong>: Controlled Ag migration enables nanoscale filamentary switching with low operating voltages (&lt;3 V).</div><div><strong>High-frequency capacitors</strong>: Stable ε′ and low tanδ up to 1 MHz meet demands for 5G/6G integrated passives.</div><div><strong>Flexible electronics</strong>: Compatibility with polymer hybrids (e.g., PVA-SiO₂) allows integration into stretchable substrates.</div><div>Challenges such as interfacial defect control and thermal stability are addressed, with proposed solutions including barrier layers and stoichiometric optimization. This work bridges fundamental dielectric spectroscopy with practical device engineering, offering a roadmap for advancing Ag/Al/SiO₂/Si/Ag structures in nanoelectronics and beyond.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109256"},"PeriodicalIF":1.4,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar ,&nbsp;Deven H. Patil ,&nbsp;Khushi Jain ,&nbsp;Ankit Dixit ,&nbsp;Naveen Kumar ,&nbsp;Vihar Georgiev ,&nbsp;S. Dasgupta ,&nbsp;Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":"10.1016/j.sse.2025.109254","url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V_th), ON current (I_ON), and OFF current (I_OFF) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L_EXT), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV_th) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L_EXT, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiNx RRAMs performance with different stoichiometries","authors":"A.E. Mavropoulis ,&nbsp;G. Pissanos ,&nbsp;N. Vasileiadis ,&nbsp;P. Normand ,&nbsp;G.Ch. Sirakoulis ,&nbsp;P. Dimitrakis","doi":"10.1016/j.sse.2025.109252","DOIUrl":"10.1016/j.sse.2025.109252","url":null,"abstract":"<div><div>The microstructure of SiN_x is strongly affected by its stoichiometry, x. The stoichiometry of SiN_x thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109252"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit","authors":"Keerthana Shajil Nair ,&nbsp;Muhammad Hamid Raza ,&nbsp;Catherine Dubourdieu ,&nbsp;Veeresh Deshpande","doi":"10.1016/j.sse.2025.109255","DOIUrl":"10.1016/j.sse.2025.109255","url":null,"abstract":"<div><div>Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf_0.5Zr_0.5O₂ (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm² at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109255"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}