Solid-state Electronics最新文献

Temperature-dependence of current gain and turn-on voltages of GaAs-based HBTs with different base layers grown by MOCVD MOCVD生长不同基层gaas基hbt电流增益和导通电压的温度依赖性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-16 DOI: 10.1016/j.sse.2025.109180

Zhen Liu , ShuQing Deng , JianPing Liu , Yong Huang , Hui Yang

引用次数: 0

Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG 可解释人工智能在基于深度学习的门长可扩展IV参数提取器中的应用

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-14 DOI: 10.1016/j.sse.2025.109154

Fredo Chavez , Jen-Hao Chen , Chien-Ting Tung , Chenming Hu , Sourabh Khandelwal

{"title":"Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG","authors":"Fredo Chavez , Jen-Hao Chen , Chien-Ting Tung , Chenming Hu , Sourabh Khandelwal","doi":"10.1016/j.sse.2025.109154","DOIUrl":"10.1016/j.sse.2025.109154","url":null,"abstract":"<div><div>A new deep-learning(DL) based gate length scalable I-V parameter extraction technique for FDSOI technology on industry-standard BSIM-IMG compact model is presented. For the first time, the learning quality of DL extractors has been studied using an explainable AI technique called SHapley Additive exPlanations (SHAP). Through analysis, it is shown that the single-step DL parameter extraction can get deviated by less relevant relationships between the <span><math><mrow><mi>I</mi><mo>−</mo><mi>V</mi></mrow></math></span> region and the BSIM-IMG parameters. A multi-step DL extraction is then designed by applying expertise in BSIM-IMG model parameters. The multi-step DL extractor has a customized DL architecture that forces the DL model to learn the relevant relationship between the input <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></math></span> datapoint and the BSIM-IMG parameters. The single- and multi-step DL extraction has been tested for measured data with gate-lengths (<span><math><msub><mrow><mi>L</mi></mrow><mrow><mi>G</mi></mrow></msub></math></span>) ranging from 52 nm to 961 nm. The multi-step DL extractor shows better accuracy in I-V and better scaling to the key electrical parameters as compared to the single-step DL parameter extraction. The developed solution has improved the accuracy, shortened extraction time, reduced the complexity, and can assist in very fast scalable model generation for FDSOI technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109154"},"PeriodicalIF":1.4,"publicationDate":"2025-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144307232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mobility and intrinsic performance of silicon-based nanosheet FETs at 3 nm CMOS and beyond 3纳米及以上的硅基纳米片场效应管的迁移率和内在性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-13 DOI: 10.1016/j.sse.2025.109172

Ankit Dixit , Ali Rezaei , Nikolas Xeni , Naveen Kumar , Tapas Dutta , Ismail Topaloglu , Preslav Aleksandrov , Asen Asenov , Vihar Georgiev

引用次数: 0

Impact of Device Layout on Self-Heating Extraction in MOSFETs 器件布局对mosfet自热萃取的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-09 DOI: 10.1016/j.sse.2025.109175

Arka Halder, Martin Vanbrabant, Dimitri Lederer, Jean-Pierre Raskin, Valeriya Kilchytska

{"title":"Impact of Device Layout on Self-Heating Extraction in MOSFETs","authors":"Arka Halder, Martin Vanbrabant, Dimitri Lederer, Jean-Pierre Raskin, Valeriya Kilchytska","doi":"10.1016/j.sse.2025.109175","DOIUrl":"10.1016/j.sse.2025.109175","url":null,"abstract":"<div><div>This work analyses the impact of device layout on self-heating (SH) extraction and treats it in terms of parasitic series resistance and heat evacuation paths. Specifically, the impact of having four-terminal (4T) gate access structures used in gate resistance technique for SH characterization is investigated. To evaluate the SH parameters, the RF characterization technique is utilized, which includes measuring S-parameters over a wide frequency range. Two devices are compared in this study based on the same core MOSFET: one with the 4T gate access structure and one without these additional accesses. It is experimentally demonstrated that a lower thermal resistance is observed for the 4T device. Apart from cooling through the 4T gate accesses which could explain this observation, it is seen that parasitic series resistances could also affect the extraction of thermal resistance through the RF technique. Through PDK simulations, the impact of the series resistances on SH extraction using the RF technique is explored further. The fact that even for the same core device the layout can affect the extracted thermal parameters is evidenced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109175"},"PeriodicalIF":1.4,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Dual-Technology FET: nMOS/pTFET in the same device 双技术FET: nMOS/pTFET在同一器件中

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-08 DOI: 10.1016/j.sse.2025.109177

C.A.B. Mori , P.H. Duarte , R.C. Rangel , P.G.D. Agopian , J.A. Martino

引用次数: 0

Low-loss silicon substrates with PN passivation in 28 nm FD-SOI 28 nm FD-SOI中PN钝化的低损耗硅衬底

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-08 DOI: 10.1016/j.sse.2025.109174

M. Rack , M. Nabet , Y. Bendou , M. Vanbrabant , M. Moulin , Q. Courte , S. Cremer , A. Cathelin , D. Lederer , J.-P. Raskin

引用次数: 0

Experimental extraction of self-heating in SOI nanowire MOSFETs at cryogenic temperatures 低温下SOI纳米线mosfet自热的实验提取

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-08 DOI: 10.1016/j.sse.2025.109176

Flavio Enrico Bergamaschi , Jefferson Almeida Matos , Jaime Calçade Rodrigues , Giovanni Almeida Matos , Michelly de Souza , Sylvain Barraud , Mikael Cassé , Olivier Faynot , Marcelo Antonio Pavanello

引用次数: 0

Model of threshold voltage and drain current in core-shell junctionless transistor on FD-SOI FD-SOI上无核壳结晶体管的阈值电压和漏极电流模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-08 DOI: 10.1016/j.sse.2025.109173

Cunhua Dou , Weijia Song , Yu Yan , Xuan Zhang , Zhiyu Tang , Binhong Li , Yong Xu , Sorin Cristoloveanu

引用次数: 0

Characteristics evaluation of reverse blocking diode thyristor for DC circuit breaker 直流断路器用反向阻断二极管晶闸管特性评价

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-04 DOI: 10.1016/j.sse.2025.109163

Zhengheng Qing, Lin Liang, Mosai Xu

{"title":"Characteristics evaluation of reverse blocking diode thyristor for DC circuit breaker","authors":"Zhengheng Qing, Lin Liang, Mosai Xu","doi":"10.1016/j.sse.2025.109163","DOIUrl":"10.1016/j.sse.2025.109163","url":null,"abstract":"<div><div>In this paper, the fast turn-off ability and series characteristics of reverse blocking diode thyristor are evaluated for DC circuit breakers. The turn-off operation mechanism of RBDT is simulated in Sentaurus TCAD. Besides, it is discussed the influence of the structure parameter and carrier lifetime on the transient characteristics of RBDT. The current distribution during the turn-off process of RBDT is uniform which indicates a small possibility of the occurrence of the turn-off failure. A fast turn-off speed could be achieved by the reduction of the P base thickness, doping concentration and carrier lifetime without compromising the turn-on characteristics. The fast turn-off capability and series characteristics are also investigated by experiments. It is shown that RBDT could be turned off within several microseconds. Besides, the voltage allocation between each RBDT is proportional to the breakdown voltage, which manifests the voltage balance equipment could be removed. Besides, RBDT can turn on at low voltage condition (25 V) with low switching loss. The excellent device performance makes RBDT a prospective candidate for DC circuit breaker applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109163"},"PeriodicalIF":1.4,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144240333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of N-type substrate’s bias potential on electrical characteristics of 4H-SiC integrated devices for All-SiC ICs n型衬底偏置电位对全sic集成电路中4H-SiC集成器件电特性的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-06-04 DOI: 10.1016/j.sse.2025.109155

Yongjia Li, Guiqiang Zheng, Jie Ma, Yong Gu, Jiaxing Wei, Sheng Li, Long Zhang, Siyang Liu, Weifeng Sun

{"title":"Influence of N-type substrate’s bias potential on electrical characteristics of 4H-SiC integrated devices for All-SiC ICs","authors":"Yongjia Li, Guiqiang Zheng, Jie Ma, Yong Gu, Jiaxing Wei, Sheng Li, Long Zhang, Siyang Liu, Weifeng Sun","doi":"10.1016/j.sse.2025.109155","DOIUrl":"10.1016/j.sse.2025.109155","url":null,"abstract":"<div><div>In this paper, the influence of N-type substate’s bias potential on electrical characteristics of 4H Silicon carbide (SiC) integrated devices for all-SiC monolithic ICs are investigated by measurements and simulations. The devices were fabricated on 4H-SiC (0001) wafer with N-type substrate and P-type epitaxial layer. The measurement results show that changing bias potential of N-type substrate has significant effect on on-state <em>BV</em> (<em>BV<sub>ON</sub></em>) and off-state <em>BV</em> (<em>BV<sub>OFF</sub></em>) for high-voltage devices. Technology computer aided design (TCAD) simulations are carried out to give insight into the mechanism of the influence of substrate’s bias potential. In mechanism revealing, the connection type of substrate is divided into three modes: (i) grounded substate mode, (ii) floating substate mode, (iii) high-voltage substate mode, and different connection modes results in different depletion types in drift region, which in turn affects <em>BV<sub>ON</sub></em> and <em>BV<sub>OFF</sub></em>.</div><div>By comparison, floating substrate is the best choose among three connection modes mentioned above for high-voltage SiC devices. Based on the revealed influence mechanisms of substate’s bias potential, an efficient method to eliminate the influence of N-type substate’s bias potential is proposed in this paper, which results in stable and high <em>BV<sub>ON</sub></em> and <em>BV<sub>OFF</sub></em>.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109155"},"PeriodicalIF":1.4,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144229829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0