Solid-state Electronics最新文献

{"title":"Enhancing ultra-thin-barrier AlGaN/GaN HEMTs with LPCVD SiN passivation for high-power applications","authors":"Jui-Sheng Wu ,&nbsp;Chen-Hsi Tsai ,&nbsp;You-Chen Weng ,&nbsp;Edward Yi Chang","doi":"10.1016/j.sse.2025.109260","DOIUrl":"10.1016/j.sse.2025.109260","url":null,"abstract":"<div><div>Ultra-thin-barrier AlGaN/GaN HEMTs offer a gate-recess-free solution but suffer from high on-resistance and current degradation. In this work, ultra-thin-barrier AlGaN/GaN heterostructures with a 1-nm GaN cap and 5-nm Al_0.22Ga_0.78N barrier were fabricated, followed by LPCVD SiN passivation of four different thicknesses (50, 60, 150, and 220 nm) to solve the low carrier density issues associated with thin-barrier structures. The 220 nm LPCVD-SiN passivated device achieves a high <em>I</em>_D,max of 907 mA/mm and the lowest on-resistance of 8.9 Ω·mm. In addition, to evaluate the stability of current output, thinner LPCVD-SiN layers exhibit better current stability under ON-state stress up to 150 °C. These findings highlight the benefits of ultra-thin-barrier AlGaN/GaN HEMTs design for future high-power GaN applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109260"},"PeriodicalIF":1.4,"publicationDate":"2025-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels","authors":"N. Paul ,&nbsp;S. Chattopadhyay","doi":"10.1016/j.sse.2025.109259","DOIUrl":"10.1016/j.sse.2025.109259","url":null,"abstract":"<div><div>The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10⁻⁴ μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10⁻⁷ μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109259"},"PeriodicalIF":1.4,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physics-based compact model of subband energy for GAAFETs including corner rounding and geometric variability analysis utilizing Monte Carlo simulation","authors":"Swapna Sarker,&nbsp;Abhishek Kumar,&nbsp;Avirup Dasgupta","doi":"10.1016/j.sse.2025.109253","DOIUrl":"10.1016/j.sse.2025.109253","url":null,"abstract":"<div><div>We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109253"},"PeriodicalIF":1.4,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Colossal permittivity and defect-engineered conduction in Ag/Al/SiO2/Si/Ag MIS structures for next-generation RRAM and 5G/6G capacitors","authors":"A. Ashery","doi":"10.1016/j.sse.2025.109256","DOIUrl":"10.1016/j.sse.2025.109256","url":null,"abstract":"<div><div>The Ag/Al/SiO₂/Si/Ag metal–insulator-semiconductor (MIS) structure exhibits remarkable dielectric and electrical properties, making it a promising candidate for next-generation electronic applications. This study systematically investigates the colossal permittivity, defect-mediated conduction, and relaxation dynamics of the dual-metal MIS structure using impedance spectroscopy, dielectric analysis, and AC conductivity measurements across wide frequency (1 kHz–20 MHz), temperature (80–400 K), and voltage (±5 V) ranges. Key findings reveal that the Ag/Al electrode configuration induces unique interfacial polarization effects, leading to ultrahigh dielectric constants (ε′ &gt; 103 at low frequencies) and low loss tangents (tanδ &lt; 0.1) suitable for high-frequency capacitors in 5G/6G technologies. The structure also demonstrates voltage-tunable resistive switching via Ag filament formation, enabling ultra-low-power resistive random-access memory (RRAM) with enhanced endurance.</div><div>Novelty: Unlike conventional Al/SiO₂/Si devices, the dual-metal design leverages Ag’s high ionic mobility to modulate defect states and conduction pathways, resulting in: Colossal permittivity from space charge polarization at Ag/SiO₂ and SiO₂/Si interfaces. Defect-engineered conduction via thermally activated hopping and Fowler-Nordheim tunneling. Negative capacitance effects at high frequencies, attributed to charge trapping/detrapping dynamics.</div><div>New Applications:</div><div><strong>RRAM</strong>: Controlled Ag migration enables nanoscale filamentary switching with low operating voltages (&lt;3 V).</div><div><strong>High-frequency capacitors</strong>: Stable ε′ and low tanδ up to 1 MHz meet demands for 5G/6G integrated passives.</div><div><strong>Flexible electronics</strong>: Compatibility with polymer hybrids (e.g., PVA-SiO₂) allows integration into stretchable substrates.</div><div>Challenges such as interfacial defect control and thermal stability are addressed, with proposed solutions including barrier layers and stoichiometric optimization. This work bridges fundamental dielectric spectroscopy with practical device engineering, offering a roadmap for advancing Ag/Al/SiO₂/Si/Ag structures in nanoelectronics and beyond.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109256"},"PeriodicalIF":1.4,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar ,&nbsp;Deven H. Patil ,&nbsp;Khushi Jain ,&nbsp;Ankit Dixit ,&nbsp;Naveen Kumar ,&nbsp;Vihar Georgiev ,&nbsp;S. Dasgupta ,&nbsp;Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":"10.1016/j.sse.2025.109254","url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V_th), ON current (I_ON), and OFF current (I_OFF) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L_EXT), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV_th) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L_EXT, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiNx RRAMs performance with different stoichiometries","authors":"A.E. Mavropoulis ,&nbsp;G. Pissanos ,&nbsp;N. Vasileiadis ,&nbsp;P. Normand ,&nbsp;G.Ch. Sirakoulis ,&nbsp;P. Dimitrakis","doi":"10.1016/j.sse.2025.109252","DOIUrl":"10.1016/j.sse.2025.109252","url":null,"abstract":"<div><div>The microstructure of SiN_x is strongly affected by its stoichiometry, x. The stoichiometry of SiN_x thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109252"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evidence of out-of-equilibrium body potential in undoped EZ-FET","authors":"Abbas Hamzeh ,&nbsp;Maryline Bawedin ,&nbsp;Nada Zerhouni Abdou ,&nbsp;Miltiadis Alepidis ,&nbsp;Pablo Acosta-Alba ,&nbsp;Laurent Brunet ,&nbsp;Irina Ionica","doi":"10.1016/j.sse.2025.109251","DOIUrl":"10.1016/j.sse.2025.109251","url":null,"abstract":"<div><div>In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109251"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145118393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of Self-Heating effect between SOI and SOS MOSFETs","authors":"Run-Song Dou ,&nbsp;Jia-Min Li ,&nbsp;Fan-Yu Liu ,&nbsp;Hui-ping Zhu ,&nbsp;Bo Li ,&nbsp;Jiang-Jiang Li ,&nbsp;Bao-Gang Sun ,&nbsp;Yang Huang ,&nbsp;Jing Wan ,&nbsp;Yong Xu ,&nbsp;Zheng-sheng Han ,&nbsp;Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109250","DOIUrl":"10.1016/j.sse.2025.109250","url":null,"abstract":"<div><div>In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109250"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145096281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on drain bias dependence of Y-parameters under on-state condition in GaN HEMTs using low-frequency vector network analyzer and device simulation","authors":"Toshiyuki Oishi ,&nbsp;Ken Kudara ,&nbsp;Yutaro Yamaguchi ,&nbsp;Shintaro Shinjo ,&nbsp;Koji Yamanaka ,&nbsp;Saga University ,&nbsp;Mitsubishi Electric Corporation","doi":"10.1016/j.sse.2025.109245","DOIUrl":"10.1016/j.sse.2025.109245","url":null,"abstract":"<div><div>The drain bias dependence of low-frequency Y-parameters under on-state conditions in Gallium Nitride high electron mobility transistors (GaN HEMTs) is investigated using experimental results and device simulation. The Y-parameters for broadband frequencies from 10 Hz to 100 MHz were systematically measured using a vector network analyzer for drain voltage from 3 to 30 V at the gate voltage of 0 V from room temperature to 120 degrees Celsius. Six signals with the peaks were observed in the imaginary parts (Im) of Y₂₂ and Y₂₁. These peaks were categorized into two groups. One is that the peaks appeared around 5 MHz and have negative slopes in Arrhenius plots. Another is that the peaks appeared below 150 kHz and have an activation energy that can be estimated from Arrhenius plots. The second group was further divided into peaks appeared in both Im(Y₂₂) and Im(Y₂₁), and those that appeared only in Im(Y₂₁). The device simulation including self-heating effects was performed using the trap parameters estimated from the experimental results. Both DC and Y-parameter characteristics for the simulation have good agreement with the experimental results. By the simulation for the individual effects, the peaks around 5 MHz result from the heat generation in GaN HEMTs. The peaks below 150 kHz are considered to originate from the traps in AlGaN and GaN layers. The traps in the GaN layer generate the peaks in both Im(Y₂₂) and Im(Y₂₁), while the traps in the AlGaN layer generate peaks in only Im(Y₂₁).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109245"},"PeriodicalIF":1.4,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145096282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ZnPc-based schottky diodes: Effect of amorphous polymer interlayers on electrical and structural properties","authors":"Nargis Khatun ,&nbsp;Sumona Sinha ,&nbsp;A.K.M. Maidul Islam","doi":"10.1016/j.sse.2025.109249","DOIUrl":"10.1016/j.sse.2025.109249","url":null,"abstract":"<div><div>This study investigates the influence of Indium Tin Oxide (ITO) electrode surface modification on the electrical properties of zinc phthalocyanine (ZnPc)– based Schottky diodes, using amorphous polymers, specifically polystyrene (Ps) and poly(butyl methacrylate) (PBMA). Devices with configurations of Al (Aluminum)/ZnPc/ITO, Al/ZnPc/Ps/ITO, and Al/ZnPc/PBMA/ITO were fabricated and analysed through current–voltage (I-V) characterisation. Devices modified with polymers showed significantly improved electrical performance, with the rectification ratio rising from 0.81 (pure ZnPc) to 4.24 for ITO modified with PBMA and 6.32 for ITO modified with Ps, along with optimised ideality factors and reduced series resistance. Space-charge-limited conduction (SCLC) became dominant, indicating enhanced charge mobility in the modified devices. UV–Vis analysis further confirmed this improvement, showing that PBMA modification enhances π–π* interactions and molecular aggregation within ZnPc thin films, reducing the optical bandgap from 3.05 eV to 2.75 eV (Ps) and 2.68 eV (PBMA), which indicates modified electronic properties due to polymer incorporation. Structural investigations employing XRR and AFM complement these findings, demonstrating improved crystallite size and a smoother surface, which lead to better charge transport. These results highlight the efficiency of polymer surface modification in enhancing ZnPc-based Schottky diodes, presenting intriguing possibilities for future optoelectronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109249"},"PeriodicalIF":1.4,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}