B. Martinez , B. Bertrand , Y.-M. Niquet , M. Vinet
{"title":"Superimposed two-contact gate stacks for an improved electrostatic control of Si spin qubits","authors":"B. Martinez , B. Bertrand , Y.-M. Niquet , M. Vinet","doi":"10.1016/j.sse.2025.109178","DOIUrl":"10.1016/j.sse.2025.109178","url":null,"abstract":"<div><div>Spin qubits based on gate-defined quantum dots require a tight electrostatic control all along the active layer. Large-scale multi-qubit devices must enable an individual control over the tunnel coupling of neighbor QD pairs to perform two-qubit gates and spin readout. Here we propose a small modification of the widely used TiN/Polysilicon gate stack that offers an extra required control knob for the tunnel coupling while preserving the gate pitch. We define the relevant metrics for the tunnel control, perform 3D device simulations coupled to a toy model to optimize the device layout, and demonstrate that such a gate stack represents a scalable building block for large-scale one-dimensional spin qubit arrays.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109178"},"PeriodicalIF":1.4,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144522970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Perrosé , P. Acosta , J. Lugo-Alvarez , A.M. Papon , X. Garros , J.P. Raskin
{"title":"Low-loss RF substrate compatible with FD-SOI integration using Si+ implantation","authors":"M. Perrosé , P. Acosta , J. Lugo-Alvarez , A.M. Papon , X. Garros , J.P. Raskin","doi":"10.1016/j.sse.2025.109189","DOIUrl":"10.1016/j.sse.2025.109189","url":null,"abstract":"<div><div>The fabrication of localized passivation layers combining Si<sup>+</sup> ion implantation and thermal annealing was explored. Using metallic coplanar waveguides, key performance metrics such as harmonic distortion and effective resistivity were extracted and analyzed. We demonstrated that the post-implantation thermal annealing temperature had a significant impact on Radio-Frequency performances. The optimum RF performances were obtained at an annealing temperature of 600 °C. This behavior was explained with photoluminescence and TEM characterization that revealed the presence of interstitial clusters. As it can be used locally, this method should enable the co-integration of Fully Depleted Silicon-on-Insulator (FD-SOI) technology with high-quality RF circuitry, leveraging the advantageous HR properties of the base Si substrate.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109189"},"PeriodicalIF":1.4,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144514018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Noel , V. Larrey , S. Tardif , F. Rieutord , D. Landru , F. Fournel
{"title":"Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing","authors":"P. Noel , V. Larrey , S. Tardif , F. Rieutord , D. Landru , F. Fournel","doi":"10.1016/j.sse.2025.109188","DOIUrl":"10.1016/j.sse.2025.109188","url":null,"abstract":"<div><div>Direct hydrophilic bonding of silicon structures with low dielectric thickness may lead to the generation of bonding voids during annealing. Yet, silicon layer transfer requires thinner dielectric layers for FD–SOI and C-FET advanced devices. The aim being high bond strengths and low bonding void densities for advanced technological nodes, we show the crucial impact of bonding layer properties on interface sealing and bonding energies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109188"},"PeriodicalIF":1.4,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144500845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhong Pan , Yeojin Jeong , MengMeng Chu , Yunhui Jang , Fucheng Wang , Jingwen Chen , Yong-Sang Kim , Jang-Kun Song , Muhammad Quddamah Khokhar , Junsin Yi
{"title":"Enhancing the mobility of p-type SnOx thin-film transistors through doping and plasma treatment","authors":"Zhong Pan , Yeojin Jeong , MengMeng Chu , Yunhui Jang , Fucheng Wang , Jingwen Chen , Yong-Sang Kim , Jang-Kun Song , Muhammad Quddamah Khokhar , Junsin Yi","doi":"10.1016/j.sse.2025.109181","DOIUrl":"10.1016/j.sse.2025.109181","url":null,"abstract":"<div><div>P-type semiconductors are less common than their n-type counterparts, and their performance often lags in comparison, which hinders the efficiency of electronic devices. In this study, we demonstrate a two-step approach to enhance the performance of tin oxide based thin-film transistors (TFTs) by combining aluminum (Al) doping and hydrogen plasma treatment. The Al doping significantly enhanced the field-effect mobility of the SnO<sub>x</sub> films, while the hydrogen plasma treatment enabled the transition to p-type conductivity. The fabricated p-type Al-doped SnO<sub>x</sub> TFTs exhibited a threshold voltage of −5.2 V, a field-effect mobility of 1.17 cm<sup>2</sup>/V·s, and I<sub>on</sub>/I<sub>off</sub> of 10<sup>5</sup>. This work provides a novel strategy for optimizing the performance of p-type SnO<sub>x</sub> semiconductors, contributing to the development of low-power complementary metal-oxide semiconductor (CMOS) technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109181"},"PeriodicalIF":1.4,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dongbin Kim , Jongsu Baek , Yoonho Choi , Junghun Kim , Hyoung Woo Kim , Byung Jin Cho
{"title":"Self-aligned nitrogen doping via plasma treatment of NiO/β-Ga2O3 heterojunction diodes","authors":"Dongbin Kim , Jongsu Baek , Yoonho Choi , Junghun Kim , Hyoung Woo Kim , Byung Jin Cho","doi":"10.1016/j.sse.2025.109182","DOIUrl":"10.1016/j.sse.2025.109182","url":null,"abstract":"<div><div>In this work, we demonstrate a novel doping process via self-aligned nitrogen (SA-N<sub>2</sub>) plasma treatment of the NiO/β-Ga<sub>2</sub>O<sub>3</sub> heterojunction diodes. The SA-N<sub>2</sub> plasma-treated heterojunction diodes exhibit improved breakdown voltage from 1080 V to 1731 V while maintaining a high on–off ratio (<em>I<sub>ON</sub>/I<sub>OFF</sub></em>) exceeding 10<sup>11</sup> and achieving a reduced specific on-resistance (<em>R<sub>on.sp</sub></em>). It is found that the SA-N<sub>2</sub> plasma treatment forms a resistive region acting as a shallow guard ring in the β-Ga<sub>2</sub>O<sub>3</sub> around the anode. It is also confirmed that doped N plays the role of both a shallow acceptor and a deep acceptor in NiO and β-Ga<sub>2</sub>O<sub>3</sub>, respectively. This process can be easily and cost-effectively applied to the heterojunction structure, contributing to further performance improvement of the wide bandgap power device.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109182"},"PeriodicalIF":1.4,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144491937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qian Bo-Han, Sun Jiu-Xun, Wei Chan, Li Yang, Cui Hai-Juan, Yang Hong-Chun
{"title":"Analytic model for organic field-effect transistors based on Vissenberg-Matters mobility model","authors":"Qian Bo-Han, Sun Jiu-Xun, Wei Chan, Li Yang, Cui Hai-Juan, Yang Hong-Chun","doi":"10.1016/j.sse.2025.109183","DOIUrl":"10.1016/j.sse.2025.109183","url":null,"abstract":"<div><div>The fundamental <em>I</em>–<em>V</em> formula of an organic field effect transistor (OFET) is reformulated as double integral of mobility function by using the Poisson’s equation. The reformulated <em>I</em>–<em>V</em> formula overcome the divergence of the integrand in original <em>I</em>–<em>V</em> formula and is convenient not only for further analytic derivations but also for numerical calculations. An analytic binomial expansion for arbitrary power is proposed to analytically derive the OFET model based on Vissenberg-Matters (VM) mobility model being able to consider all terms deduced from the completed VM model. The numerical calculations for six OFET made of four kinds of materials show that the matching degree between theoretical <em>I</em>–<em>V</em> curves and the experimental data is satisfactory for completed model, but evident deviations for <em>I<sub>D</sub></em>–<em>V<sub>D</sub></em> curves exhibited in usual treatment that only considering first term deduced from the VM model. It is important to consider all terms in modelling OFET to ensure accuracy and reliability for extraction of parameters. These are useful for practical applications and device simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109183"},"PeriodicalIF":1.4,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces","authors":"Hao-En Cheng , Ching-Lin Wu , Chun-Yu Lin","doi":"10.1016/j.sse.2025.109185","DOIUrl":"10.1016/j.sse.2025.109185","url":null,"abstract":"<div><div>In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109185"},"PeriodicalIF":1.4,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hong Zhang , Chao Peng , Teng Ma , Zhan-Gang Zhang , Yu-Juan He , Bin Li , Zhi-Feng Lei
{"title":"Investigation of heavy-ion induced degradation and catastrophic burnout mechanism in SiC diode","authors":"Hong Zhang , Chao Peng , Teng Ma , Zhan-Gang Zhang , Yu-Juan He , Bin Li , Zhi-Feng Lei","doi":"10.1016/j.sse.2025.109184","DOIUrl":"10.1016/j.sse.2025.109184","url":null,"abstract":"<div><div>Irradiation experiment and simulation of 205-MeV Ge ion and 283-MeV I ion were used to analyze the single event leakage current (SELC) and the single event burnout (SEB) mechanism of SiC diode. Under two selected heavy ion irradiations, the ampere-magnitude pulse current were generated along with the occurrence of SEB. The SEB area was found to cover the anode metal, epitaxial layer and substrate in microscopic analysis, which resulted in damage to the forward and reverse characteristics of device. Devices were irradiated by 205-MeV Ge ion with a fluence of 5 × 10<sup>6</sup> n·cm<sup>−2</sup>, under 200 V and 300 V reverse bias voltages, the breakdown voltage were degraded by 70 % and 82 % respectively. The anode contacts of SELC devices had local fractures and displacements, which led to the degradation of breakdown characteristics. Combined Monte Carlo simulation and TCAD simulation, the SEB critical temperature appeared near the anode contact firstly when the two selected heavy ions were incident. When the two selected heavy ions were incident from Schottky and Ohmic contacts at a bias voltage of 200 V, excessive temperature in local areas and temperature differences between different anode materials caused the fractures and displacements of anode contact.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109184"},"PeriodicalIF":1.4,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhen Liu , ShuQing Deng , JianPing Liu , Yong Huang , Hui Yang
{"title":"Temperature-dependence of current gain and turn-on voltages of GaAs-based HBTs with different base layers grown by MOCVD","authors":"Zhen Liu , ShuQing Deng , JianPing Liu , Yong Huang , Hui Yang","doi":"10.1016/j.sse.2025.109180","DOIUrl":"10.1016/j.sse.2025.109180","url":null,"abstract":"<div><div>Temperature-dependence of GaAs-based heterojunction bipolar transistors with GaAs, InGaAs and GaAsSb base layers were investigated. HBT with InGaAs base was found to have the best thermal stability of current gain of <em>Δβ/ΔT</em> = −0.0828/K. Both valence-band offset (<em>ΔE<sub>V</sub></em>) of emitter–base junction and defects activation energy (<em>ΔE<sub>a</sub></em>) of base layer were accounted for the low <em>Δβ/ΔT</em> coefficient by fitting the relationship between <em>1/β</em> and <em>1/T</em> using a proposed model. In addition, lower turn-on voltages of 1.038 V and 1.036 V were extracted for HBTs with narrower bandgap InGaAs and GaAsSb bases, respectively, in contrast to 1.075 V in HBT with GaAs base.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109180"},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144314133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG","authors":"Fredo Chavez , Jen-Hao Chen , Chien-Ting Tung , Chenming Hu , Sourabh Khandelwal","doi":"10.1016/j.sse.2025.109154","DOIUrl":"10.1016/j.sse.2025.109154","url":null,"abstract":"<div><div>A new deep-learning(DL) based gate length scalable I-V parameter extraction technique for FDSOI technology on industry-standard BSIM-IMG compact model is presented. For the first time, the learning quality of DL extractors has been studied using an explainable AI technique called SHapley Additive exPlanations (SHAP). Through analysis, it is shown that the single-step DL parameter extraction can get deviated by less relevant relationships between the <span><math><mrow><mi>I</mi><mo>−</mo><mi>V</mi></mrow></math></span> region and the BSIM-IMG parameters. A multi-step DL extraction is then designed by applying expertise in BSIM-IMG model parameters. The multi-step DL extractor has a customized DL architecture that forces the DL model to learn the relevant relationship between the input <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></math></span> datapoint and the BSIM-IMG parameters. The single- and multi-step DL extraction has been tested for measured data with gate-lengths (<span><math><msub><mrow><mi>L</mi></mrow><mrow><mi>G</mi></mrow></msub></math></span>) ranging from 52 nm to 961 nm. The multi-step DL extractor shows better accuracy in I-V and better scaling to the key electrical parameters as compared to the single-step DL parameter extraction. The developed solution has improved the accuracy, shortened extraction time, reduced the complexity, and can assist in very fast scalable model generation for FDSOI technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109154"},"PeriodicalIF":1.4,"publicationDate":"2025-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144307232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}