Solid-state Electronics最新文献

{"title":"Analog behavior of forksheet FET at high temperatures","authors":"Joao Antonio Martino ,&nbsp;Paula Ghedini Der Agopian ,&nbsp;Julius Andretti Peixoto Pires de Paula ,&nbsp;Romain Ritzenthaler ,&nbsp;Hans Mertens ,&nbsp;Anabela Veloso ,&nbsp;Naoto Horiguchi","doi":"10.1016/j.sse.2025.109139","DOIUrl":"10.1016/j.sse.2025.109139","url":null,"abstract":"<div><div>This work presents an experimental study of the analog behavior of forksheet FET from room up to 150 °C with channel lengths of 26 and 70 nm. These devices present a Zero Temperature-Coefficient (ZTC) point for a gate voltage around 0,59 V (V_ZTC) in saturation region. The threshold voltage variation with temperature (dV_T/dT) is around −0,5mV/^oC due to the Fermi level decrease. The DIBL increases with temperature but it is kept lower than 51 mV/V in the studied temperature range. The transconductance and output conductance decrease (mainly due the mobility degradation) which results in a good intrinsic voltage gain of around 36 dB at room temperature, showing a slight change (±2dB) in the studied temperature range. The maximum unity gain frequency estimated for L = 26 nm is around 358 GHz in strong inversion regime. The results show that the forksheet FETs present a good performance for analog applications at high temperature, which in addition to the already known savings in footprint area compared to nanosheet technology, are potentially useful for future mixed-signal integrated circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109139"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of multiple MISHEMT conduction channels on its analog behavior","authors":"Bruno G. Canales ,&nbsp;Bruno C.S. Sanches ,&nbsp;Joao A. Martino ,&nbsp;Eddy Simoen ,&nbsp;Uthayasankaran Peralagu ,&nbsp;Nadine Collaert ,&nbsp;Paula G.D. Agopian","doi":"10.1016/j.sse.2025.109136","DOIUrl":"10.1016/j.sse.2025.109136","url":null,"abstract":"<div><div>In this paper, the multiple channels of a MISHEMT device (Metal/Si₃N₄/AlGaN/AlN/GaN − Metal-Insulator-Semiconductor High Electron Mobility Transistor) are studied regarding their impact on fundamental DC and RF figures of merit. Although most authors treat the 2DEG channel as the MISHEMT main channel, it is shown that its MOS channel contribution to the different RF parameters is of great importance on some devices. This unique characteristic makes the MISHEMT RF parameters to be dependent on both V_GS and V_DS. The 2DEG channel presents a MAG value of 15 dB that is almost independent with the 2DEG channel length. In relation to a pure 2DEG conduction, the MOS channel is responsible for a large set of analog parameters improvements. It offers an increase of about 23 dB in maximum available gain (MAG), while sustaining a high f_T and f_max for a larger range of V_GS and drain current level.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109136"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of the effective channel length of Junctionless nanowire transistors with different drain bias through the gate capacitance","authors":"Everton M. Silva ,&nbsp;Renan Trevisoli ,&nbsp;Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109134","DOIUrl":"10.1016/j.sse.2025.109134","url":null,"abstract":"<div><div>This paper analyzes through 3D numerical simulations the effective channel length (L_EFF) of Junctionless Nanowire Transistors (JNT) through the gate capacitance (C_GG) of the devices for different drain-to-source voltages (V_DS) and compares the results with a theoretical approach. In this case, there is a phenomenon of intersection through the C_GG curves for high V_DS bias (between 0.5 V and 1 V) that indicates the pinch-off regime of the JNTs. The L_EFF extraction has been done from the extrapolation of the gate capacitance in the pinch-off regime as a function of the device’s channel length (L_MASK), for different L_MASK and source and drain lengths (L_SD) for structures with lateral spacer and different doping concentrations, showing that L_EEF increases ∼ 6 nm and presents a relationship with V_DS bias and doping concentration. Finally, one comparison with the theoretical equation was done, showing that the method is a good way to extract or even estimate the effective channel length of the experimental devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109134"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143874712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reactive sputtering deposited α-MoO3 thin films for forming-free resistive random-access memory","authors":"Zeqi Guo ,&nbsp;Xiaoxu Lai ,&nbsp;Wenhui Xu ,&nbsp;Dan Sun ,&nbsp;Chi Chen","doi":"10.1016/j.sse.2025.109130","DOIUrl":"10.1016/j.sse.2025.109130","url":null,"abstract":"<div><div>In this study, α-MoO₃ thin films were prepared on single-side polished (1 0 0) silicon substrates using radio-frequency reactive sputtering. By adjusting the substrate temperature and oxygen proportion, α-MoO₃ thin films with desirable crystal phase and surface morphology were successfully grown. The substrate temperature exceeded 400℃ and the oxygen proportion of 50 % are essential for the deposition of a single-phase polycrystalline α-MoO₃ film with abundant oxygen vacancies. A resistive random-access memory (RRAM) device fabricated by the as-prepared α-MoO₃ film exhibited stable resistive switching characteristics with a forming-free behavior, achieving set/reset voltages below 0.3 V, a cycling durability over 250 cycles and an ON/OFF ratio of 10². Furthermore, I-V curve fitting analysis revealed a trap-controlled electron conduction mechanism in the RRAM device, where the high-resistance state exhibited a space-charge-limited current (SCLC) conduction mode. This study demonstrates the significant potential of radio-frequency reactive sputtering for fabricating functional materials for the application of electronic devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109130"},"PeriodicalIF":1.4,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143859921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DFT study of adsorption density of gas molecules in 2D materials","authors":"R. Ortega,&nbsp;L. Donetti,&nbsp;C. Navarro,&nbsp;C. Márquez,&nbsp;F. Gámiz","doi":"10.1016/j.sse.2025.109116","DOIUrl":"10.1016/j.sse.2025.109116","url":null,"abstract":"<div><div>In this work we explore the possibility of using a modified version of the Langmuir adsorption model to describe the adsorption of gas molecules in 2D structures. With this aim in mind, the density of adsorption of NH₃ and N₂ in MoS₂ has been calculated. In order to do that, we have performed several DFT calculations, whose results are used as inputs for the presented model. We also explore the model limitations and future applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109116"},"PeriodicalIF":1.4,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced linearity of AlGaN/GaN HEMTs via dual-gate configuration for RF amplifier applications","authors":"Haowen Guo ,&nbsp;Wenbo Ye ,&nbsp;Junmin Zhou ,&nbsp;Yitian Gu ,&nbsp;Han Gao ,&nbsp;Xinbo Zou","doi":"10.1016/j.sse.2025.109127","DOIUrl":"10.1016/j.sse.2025.109127","url":null,"abstract":"<div><div>This study investigates RF linearity performance of a GaN dual-gate HEMT, focusing on its two-tone intermodulation characteristics. The dual-gate configuration is implemented to enhance linearity performance by reducing feedback capacitance to 41.8 fF/mm, achieving a reduction of 73 % when compared to conventional single-gate HEMTs. The dual-gate device showcases a small-signal gain of 23.5 dB at 2.1 GHz, which remains constant regardless of DC gate bias voltage <em>V_B</em>. Intermodulation distortion could be mitigated by increasing <em>V_B</em>, as evidenced by device’s highest OIP3 of 30.1 dBm at <em>V_B</em> of 3 V and a drain voltage of 20 V. Additionally, the OIP3/<em>P_DC</em> reaches a peak value of 10.6 dB at <em>V_DS</em> of 5 V. A comparison between the dual-gate HEMT and a conventional single-gate device demonstrates a 3.7 dB gain increase of and a linearity improvement of 5.9 dB. These results highlight the advantageous power gain and high linearity of the dual-gate structure, indicating its considerable potential for RF amplifier applications that require minimum signal distortion.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109127"},"PeriodicalIF":1.4,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143839177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evolution of threshold voltage in 1.2-kV planar SiC MOSFETs during repetitive UIS stressing","authors":"Chaobiao Lin ,&nbsp;Ling Hong ,&nbsp;Ding Wu ,&nbsp;Na Ren ,&nbsp;Kuang Sheng","doi":"10.1016/j.sse.2025.109125","DOIUrl":"10.1016/j.sse.2025.109125","url":null,"abstract":"<div><div>In this paper, repetitive unclamped inductive switching (UIS) stressing was conducted on 1.2-kV planar silicon carbide (SiC) MOSFETs. Different off-state gate voltage biases (<em>V_gs-off</em> = 0 V/−5 V/−10 V) were applied. The evolution of on-resistance (<em>R_on</em>) and threshold voltage (<em>V_th</em>) in different conditions has been observed. It was found that <em>R_on</em> was increased and <em>V_th</em> was negatively shifted for −5 V and −10 V <em>V_gs-off</em> conditions. Failure analysis was conducted to investigate the <em>R_on</em> degradation mechanism. Aluminum (Al) melting on chip upper surface occurred during UIS stressing, which was verified by scanned-electron-beam observation. Regarding <em>V_th</em> shift, the repetitive UIS stressing applied on the devices was analyzed as a combination of high-temperature reverse bias (HTRB) stress and high-temperature gate bias (HTGB) stress. To aid the mechanism analysis, TCAD simulations of the UIS avalanche process were conducted. When negative <em>V_gs-off</em> was applied, the channel region entered an accumulated state, and the electric field was directed toward the gate oxide. This facilitated hot hole injection into the gate oxide, leading to a significant increase in positive oxide charge density. As the magnitude of the negative <em>V_gs-off</em> bias increased, the electric field stress in the gate oxide and hole density in the channel region were aggravated, resulting in a more pronounced <em>V_th</em> shift.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109125"},"PeriodicalIF":1.4,"publicationDate":"2025-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143847941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The impact of drift region length on total ionizing dose effects on LDMOSFET","authors":"Shun Li,&nbsp;Hongliang Lu,&nbsp;Jing Qiao,&nbsp;Ruxue Yao,&nbsp;Yutao Zhang,&nbsp;Yuming Zhang","doi":"10.1016/j.sse.2025.109126","DOIUrl":"10.1016/j.sse.2025.109126","url":null,"abstract":"<div><div>The adjustment of drift region length increases the design flexibility of laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) characteristics, such as breakdown voltage and on-resistance. However, its impact on the total ionizing dose (TID) effects on the device cannot be ignored. The changes in threshold voltage (<span><math><mrow><msub><mi>V</mi><mrow><mi>th</mi></mrow></msub></mrow></math></span>), transconductance (<em>g</em>_m), drain current (<span><math><mrow><msub><mi>I</mi><mi>d</mi></msub></mrow></math></span>), and on-resistance (<em>R</em>_on) of N-channel LDMOSFET (NLDMOSFET) with two different drift region lengths after TID irradiation were studied in this article. We found that the shift of <span><math><mrow><msub><mi>V</mi><mrow><mi>th</mi></mrow></msub></mrow></math></span> and <em>g</em>_m after irradiation was almost identical for both devices, whereas there was a noticeable difference in the shift of <span><math><mrow><msub><mi>I</mi><mi>d</mi></msub></mrow></math></span> and <em>R</em>_on. The influences of traps and interface states in gate oxide and field oxide on device characteristics were discussed through technology computer-aided design (TCAD). Ultimately, we discovered that the degradation of <span><math><mrow><msub><mi>V</mi><mrow><mi>th</mi></mrow></msub></mrow></math></span> after irradiation was primarily related to the gate oxide, while the degradation of drain current in linear region (<span><math><mrow><msub><mi>I</mi><mrow><mi>dlin</mi></mrow></msub></mrow></math></span>) after irradiation was mainly related to the drift region. The degradation of <em>g</em>_m and <em>R</em>_on were related to the degradation of <span><math><mrow><msub><mi>V</mi><mrow><mi>th</mi></mrow></msub></mrow></math></span> and <span><math><mrow><msub><mi>I</mi><mi>d</mi></msub></mrow></math></span>. Although the long drift region is beneficial to the breakdown and power characteristics of LDMOS devices, it causes a significant deterioration in the TID effect, which is worth considering in the design of devices and circuits applied in radiation environment.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109126"},"PeriodicalIF":1.4,"publicationDate":"2025-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143839176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electron mobility in silicon under high uniaxial strain","authors":"Nicolas Roisin,&nbsp;Loïc Lahaye,&nbsp;Jean-Pierre Raskin,&nbsp;Denis Flandre","doi":"10.1016/j.sse.2025.109118","DOIUrl":"10.1016/j.sse.2025.109118","url":null,"abstract":"<div><div>In the pursuit of improving the performance of semiconductor devices, the manipulation of material properties through strain engineering has emerged as a promising avenue. In this work, the enhancement of the electron mobility in silicon has been experimentally investigated for uniaxial strain up to almost 1% along the [100] crystal direction. The experimental data have been obtained from n-doped silicon beams strained using four-point bending scheme. To complement the experimental measurements that present a mobility enhancement of about 65%, first-principles calculations have been conducted to determine the splitting of the conduction bands and the changes in the effective masses induced by the strain. A semi-empirical model is finally used to predict the undoped behavior, which forecast a mobility increase close to 1000 cm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>V⁻¹s⁻¹ for a strain of about 1%.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109118"},"PeriodicalIF":1.4,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigating random discrete dopant-induced variability in cryogenic gate-all-around nanosheet FETs: A quantum transport simulation study","authors":"Jaehyun Lee","doi":"10.1016/j.sse.2025.109113","DOIUrl":"10.1016/j.sse.2025.109113","url":null,"abstract":"<div><div>This study investigates the variability induced by random discrete dopants (RDDs) in the source and drain extension (SDE) regions in cryogenic <span><math><mi>n</mi></math></span>-type gate-all-around nanosheet field-effect transistors using the extensive quantum transport simulations. RDDs in the SDE regions effectively alter the channel length, necessitating a detailed analysis of the temperature dependence of short channel effects across a range from cryogenic (77 K) to room temperature (300 K). The results clearly demonstrate that cryogenic devices are more susceptible to random dopant fluctuation (RDF), exhibiting greater variability in threshold voltage, ON-state current, and drain-induced barrier lowering compared to devices operating at 300 K, even when the intrinsic channel device is considered. These findings emphasize the importance of rigorously addressing local variability, such as RDF, alongside process-induced variability in the design and optimization of cryogenic devices and associated circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109113"},"PeriodicalIF":1.4,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}