Solid-state Electronics最新文献

Achieving 15.75% efficiency in solar cells: Advanced surface engineering using Tetra-Tert-Butyl-Tercarbazol-Benzonitrile and organic layer integration in n-type silicon wafer and hybrid Planar-Si systems 实现 15.75% 的太阳能电池效率：使用四叔丁基三咔唑-苯腈的先进表面工程以及 n 型硅晶片和混合平面硅系统中的有机层集成

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-11-02 DOI: 10.1016/j.sse.2024.109025

{"title":"Achieving 15.75% efficiency in solar cells: Advanced surface engineering using Tetra-Tert-Butyl-Tercarbazol-Benzonitrile and organic layer integration in n-type silicon wafer and hybrid Planar-Si systems","authors":"","doi":"10.1016/j.sse.2024.109025","DOIUrl":"10.1016/j.sse.2024.109025","url":null,"abstract":"<div><div>This study investigates the progress in n-type solar cells utilizing implanted Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) front surface fields and diffused Ag rear emitters. The n-type structure utilizes a systematic approach involving surface passivation, localized laser ablation, and screen printing, similar to commercial p-type solar cells. This design enables the conversion from p-type to n-type cell production. Ion implantation allows for accurate management of doping profiles, improving processing sequences and increasing efficiency. Analysis indicates that reduced post-implant annealing durations lead to a shallower doping profile, enhancing short-wavelength response. Its results in efficiencies reaching up to 15.75 % on large-area 200 cm2 n-type wafers. The study also examines hybrid planar-Si/organic heterojunction solar cells, emphasizing Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) to improve photovoltaic efficiency. UV–visible and fluorescence spectroscopy indicate a maximum absorption wavelength of 360 nm and an emission wavelength of 420 nm. The concentration of TTB-TB-BNZ in (4,4′-di(9H-carbazol-9-yl)-1,1′-biphenyl) (CBP) films reaches its peak effectiveness at 40–50 %, leading to notable enhancements in light absorption and charge transport. The Si/PEDOT: PSS heterojunction solar cells incorporating TTB-TB-BNZ demonstrate a power conversion efficiency (PCE) of 15.75 %. This result underscores the potential for scalable fabrication methods to improve photovoltaic performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142586195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spiro-OMeTAD Anchoring perovskite for gradual homojunction in stable perovskite solar cells 在稳定的过氧化物太阳能电池中逐步实现同质结的螺氨过氧化物锚定过氧化物

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-11-01 DOI: 10.1016/j.sse.2024.109003

{"title":"Spiro-OMeTAD Anchoring perovskite for gradual homojunction in stable perovskite solar cells","authors":"","doi":"10.1016/j.sse.2024.109003","DOIUrl":"10.1016/j.sse.2024.109003","url":null,"abstract":"<div><div>The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb<sup>2+</sup> and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142571714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band 用于射频波段 III-V/Si 单片 3D 电路的硅基集成无源器件堆栈

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109012

{"title":"Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band","authors":"","doi":"10.1016/j.sse.2024.109012","DOIUrl":"10.1016/j.sse.2024.109012","url":null,"abstract":"<div><div>In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling 栅极功函数变化对存在栅极静电耦合的多栅极鳍状硅量子点器件特性的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109013

引用次数: 0

Sputter-Deposited copper iodide thin film transistors with low Operating voltage 低工作电压的溅射沉积碘化铜薄膜晶体管

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-21 DOI: 10.1016/j.sse.2024.109014

引用次数: 0

Enhanced resistive switching performance in TiN/AlOx/Pt RRAM by high-temperature I-V cycling 通过高温 I-V 循环提高 TiN/AlOx/Pt RRAM 的电阻开关性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-15 DOI: 10.1016/j.sse.2024.109011

引用次数: 0

A well-conditioned surface potential equation for dynamically depleted SOI MOS devices accounting for the front-depletion/back-accumulation operation mode 适用于动态耗尽型 SOI MOS 器件的表面电势方程（考虑了前耗尽/后积累工作模式

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-10 DOI: 10.1016/j.sse.2024.109010

引用次数: 0

Emission cells with quantum dots on silicon chip prepared by using fs pulsed laser 利用 fs 脉冲激光在硅芯片上制备量子点发射电池

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-04 DOI: 10.1016/j.sse.2024.109009

{"title":"Emission cells with quantum dots on silicon chip prepared by using fs pulsed laser","authors":"","doi":"10.1016/j.sse.2024.109009","DOIUrl":"10.1016/j.sse.2024.109009","url":null,"abstract":"<div><div>Emission efficiency of bulk-silicon is very low due to its indirect-gap of energy band. However, it is interesting that the enhanced emission has been observed in the micro-cavities array fabricated by using femtosecond (fs) pulsed laser, in which the stimulated emission characteristics occur after annealing for suitable time in the photo-luminescence (PL) measurement at room temperature. The results of experiment and calculation demonstrated that the enhanced emission may be originated from the Si quantum dots embedded in the micro-cavities prepared by fs pulsed laser. Here, the direct-gap of energy band appears after annealing due to the Heisenberg principle related to ⊿k–1/⊿x in quantum system of nanostructures. The PL intensity obviously increases on the Si quantum dots growing with annealing for better crystallization, in which the external quantum efficiency is higher than 40 % near 760 nm. A new kind of emission source of the micro-cavities array in visible wavelength has been built on silicon wafer, in which the Si quantum dots play a main role for enhancement of emission. It should have a good application in optical integrated chip based on silicon, such as emission cells built on Si chip.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A nanophotonic approach to signal-to-noise ratio of quantum dot infrared photodetectors with surface plasmonic excitation 利用表面等离子体激发量子点红外光探测器信噪比的纳米光子方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-29 DOI: 10.1016/j.sse.2024.109008

{"title":"A nanophotonic approach to signal-to-noise ratio of quantum dot infrared photodetectors with surface plasmonic excitation","authors":"","doi":"10.1016/j.sse.2024.109008","DOIUrl":"10.1016/j.sse.2024.109008","url":null,"abstract":"<div><div>A nanophotonic approach to the signal-to-noise ratio (SNR) of an InAs-based quantum dot infrared photodetector (QDIP) with surface plasmonic excitation is reported. A 100 nm-thick Au film, perforated with a 3.1 μm-period, 2-dimensional square array of holes, referred to as a metal photonic crystal (MPC), is employed as a plasmonic coupler for it. Under the irradiance on the MPC integrated atop the QDIP, the fundamental surface plasma wave (SPW) is excited along their interface at ∼10.3 μm in wavelength. It carries the near-field that interacts with the quantum dots (QDs) under the interface. Depending on the presence of the coupler, the QDIP generates two different current–voltage (I-V) characteristics; one from the QDs normally working without MPC and the other from those coupled to the SPW near-field with it. The two I-V’s unfold the signal and noise current of each case with photoconductive gain. In their relation, generation-recombination and shot noises which are correlated with the detector signal current are directly affected by the plasmonic coupling but other sources including thermal noise are not relevant to it. Relying on these differences, the I-V analysis allows the SNR of each case and shows ∼20× enhancement by the plasmonic coupling. It reveals that most of the noise current is attributed to thermal fluctuations inherent to the quantum confinement of the QDIP. The SNR lower than the quantum efficiency in plasmonic enhancement is addressed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Smart-CX – Method of extraction of parasitic capacitances in ICs Smart-CX - 集成电路寄生电容提取方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-26 DOI: 10.1016/j.sse.2024.109007

{"title":"Smart-CX – Method of extraction of parasitic capacitances in ICs","authors":"","doi":"10.1016/j.sse.2024.109007","DOIUrl":"10.1016/j.sse.2024.109007","url":null,"abstract":"<div><div>This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>a</mi><mo>)</mo></mrow></math></span>, coupling capacitances (<span><math><mrow><mi>C</mi><mi>c</mi><mo>)</mo></mrow></math></span>, including via-to-via capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>v</mi><mo>)</mo></mrow></math></span>, contact-to-gate capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>g</mi><mo>)</mo></mrow></math></span>, contact-to-active capacitances <strong>(</strong><span><math><mrow><mi>C</mi><mi>m</mi><mi>c</mi><mo>)</mo></mrow></math></span> and fringe type capacitances with the top <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>t</mi><mo>)</mo></mrow></math></span> and bottom <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>b</mi><mo>)</mo></mrow></math></span> conductive layers.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142437856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0