Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM

As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.