Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics

This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.