Statistical analysis of random dopant fluctuation in Complementary FET

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-09-24 DOI:10.1016/j.sse.2025.109254

Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga

{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":null,"url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V<sub>th</sub>), ON current (I<sub>ON</sub>), and OFF current (I<sub>OFF</sub>) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L<sub>EXT</sub>), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV<sub>th</sub>) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L<sub>EXT</sub>, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4000,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001996","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V_th), ON current (I_ON), and OFF current (I_OFF) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L_EXT), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV_th) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L_EXT, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.

查看原文本刊更多论文

互补场效应管中随机掺杂波动的统计分析

叠层晶体管中受限通道（片）的垂直堆叠需要严格控制的几何设计，掺杂波动是决定器件可靠性的关键因素。因此，利用校准良好的TCAD模型，我们深入研究了随机掺杂波动（RDF）对互补场效应管（CFET）的影响。统计计算了阈值电压（Vth）、导通电流（ION）和关断电流（IOFF）的标准差（σ）与通道掺杂、源极/漏极（S/D）延伸区域（LEXT）、通道厚度、通道宽度和片数的关系。综合研究表明，即使在未掺杂的信道中，也观察到~ 2 mV的阈值波动（σVth），这表明RDF在LEXT中非常明显，引起了可靠性问题。因此，该分析值得深入研究，以了解未来亚2nm技术节点的cet可扩展性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.