CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-09-23 DOI:10.1016/j.sse.2025.109255

Keerthana Shajil Nair , Muhammad Hamid Raza , Catherine Dubourdieu , Veeresh Deshpande

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引用次数: 0

Abstract

Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf_0.5Zr_0.5O₂ (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm² at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.

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一晶体管一电容电路中双层铁电隧道结的CMOS后端集成

基于铁电f0.5 zr0.5 o2 （HZO）的铁电隧道结（FTJ）器件作为用于神经形态计算应用的CMOS后端可积低功耗非易失性存储器，最近引起了人们的极大兴趣。在本文中，我们展示了金属-铁电-介电-金属双层FTJ器件在180nm CMOS技术芯片后端的集成。我们介绍了集成的FTJ器件的电气特性，包括在开/关电流比为~ 18时的极化开关和电阻开关行为，以及在读取电压为1.8 V时的导通电流密度为~ 24.5 μA/cm2。此外，我们还演示了一个1-晶体管-1-电容器（1T1C）电路，通过将后端FTJ器件与前端nMOS晶体管连接，将FTJ器件的ON电流放大2.6倍。因此，我们展示了用于神经形态应用的基于hzo的FTJ器件集成的基本构建块。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.