Solid-state Electronics最新文献_第2页

Investigation of reconfigurable logic gate using integrated amorphous InGaZnO ReRAM and thin-film transistor

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-19 DOI: 10.1016/j.sse.2025.109084

Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim

{"title":"Investigation of reconfigurable logic gate using integrated amorphous InGaZnO ReRAM and thin-film transistor","authors":"Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim","doi":"10.1016/j.sse.2025.109084","DOIUrl":"10.1016/j.sse.2025.109084","url":null,"abstract":"<div><div>This paper proposes a new reconfigurable logic circuits based on InGaZnO resistive random-access memory (ReRAM) and presents a comprehensive investigation of their electrical characteristics and logic operation. Two fundamental equations that govern the transport mechanism of oxygen ions were utilized to model the formation of lateral and vertical conducting filaments in ReRAM devices in a circuit simulation environment. Based on the device models, the electrical behavior of ReRAM was examined and verified, using circuit simulators. Experimental results from dc current–voltage and pulse measurements of ReRAM and thin-film transistors (TFTs) demonstrate their electrical switching characteristics. The paper analyzes and validates the operation of two ReRAM-based logic configurations: 1 T-1 M (one transistor and one ReRAM cell) and 2 T-2 M−INV (inverter). A detailed analysis were conducted to compare the proposed ReRAM-based logic with the conventional CMOS counterparts, revealing favorable advantages in reducing transistor counts and die areas. The 1 T-1 M and 2 T-2 M−INV exhibit reconfigurable logic operations under different resistive states of ReRAM cells. Additionally, the investigations of short-circuit current profiles shows the superior performance of ReRAM-based logic gates to the CMOS counterpart in terms of power consumption. Overall, this study investigates the feasibility of ReRAM-based reconfigurable logic circuits for future low-power and high-performance computing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109084"},"PeriodicalIF":1.4,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143487699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of radiation effects of LM and UMM structure GaAs triple-junction solar cells under 1 MeV neutron irradiation

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-14 DOI: 10.1016/j.sse.2025.109087

Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken

{"title":"Comparison of radiation effects of LM and UMM structure GaAs triple-junction solar cells under 1 MeV neutron irradiation","authors":"Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken","doi":"10.1016/j.sse.2025.109087","DOIUrl":"10.1016/j.sse.2025.109087","url":null,"abstract":"<div><div>The output performances of lattice-matched (LM) and upright metamorphic (UMM) GaAs triple-junction solar cells under 1 MeV neutron irradiation were studied. The results show that the electrical performance, including open-circuit voltage, short-circuit current, maximum output power and fill factor of the solar cells were degraded seriously with the increase of neutron irradiation fluence. Meanwhile, the series resistance and the shunt resistance of solar cells are increased and decreased, respectively, when the neutron irradiation fluence increased. The degradation of maximum output power in LM and UMM GaAs cells is about the same level of 72.9 % and 72.3 % of its initial values, respectively, when the irradiation fluence is reached 6 × 10<sup>12</sup> n/cm<sup>2</sup>. By comparing the integrated current densities, it was found out that the current-limiting subcell in LM cells s always GaAs middle cell, and in the UMM cell, the current limiting unit is changed from GaInP top subcell to GaInAs middle subcell after high fluence neutron irradiation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109087"},"PeriodicalIF":1.4,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of temperature inhomogeneity and trap charge on current imbalance of SiC MOSFETs

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-12 DOI: 10.1016/j.sse.2025.109085

Chunsheng Guo, Jiapeng Li, Yamin Zhang, Hui Zhu, Meng Zhang, Shiwei Feng

引用次数: 0

Improvement of charge storage and retention characteristics of HfO2 Charge-Trapping layer in NVM based on InGaZnO channels

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-12 DOI: 10.1016/j.sse.2025.109077

Jingwen Chen , Fucheng Wang , Zhong Pan , Jang-Kun Song , Yong-Sang Kim , Muhammad Quddamah Khokhar , Junsin Yi

{"title":"Improvement of charge storage and retention characteristics of HfO2 Charge-Trapping layer in NVM based on InGaZnO channels","authors":"Jingwen Chen , Fucheng Wang , Zhong Pan , Jang-Kun Song , Yong-Sang Kim , Muhammad Quddamah Khokhar , Junsin Yi","doi":"10.1016/j.sse.2025.109077","DOIUrl":"10.1016/j.sse.2025.109077","url":null,"abstract":"<div><div>In recent years, with the widespread application of semiconductor thin-film memory devices, the focus of research has gradually shifted to how to fabricate memory with larger storage windows and longer retention times. This study employs the rapid thermal annealing (RTA) method to conduct multiple annealing treatments on charge trapping memory (CTM) devices that use HfO<sub>2</sub> as the charge trapping layer, the leakage current of the device is reduced, and the negative deviation of threshold voltage is improved. During the experiments, the charge trapping layer (CTL) and tunneling layer (TL) of the devices were deposited, and a 50 nm IGZO thin film was deposited as the channel layer. The study investigates the memory performance of TFT-NVM (thin film transistor non-volatile memory) after RTA under different conditions. The results showed that the TFT-NVM with the Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/SiO<sub>2</sub> structure has a large memory window (1.4 V) and good charge retention (>71.39 %) before O<sub>2</sub> annealing treatment. This provides a feasible approach for future research on TFT-NVM.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109077"},"PeriodicalIF":1.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Well-balanced 4H-SiC JBSFET: Integrating JBS diode and VDMOSFET characteristics for reliable 1700V applications

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-12 DOI: 10.1016/j.sse.2025.109083

Chia-Lung Hung , Yi-Kai Hsiao , Jing-Neng Yao , Hao-Chung Kuo

{"title":"Well-balanced 4H-SiC JBSFET: Integrating JBS diode and VDMOSFET characteristics for reliable 1700V applications","authors":"Chia-Lung Hung , Yi-Kai Hsiao , Jing-Neng Yao , Hao-Chung Kuo","doi":"10.1016/j.sse.2025.109083","DOIUrl":"10.1016/j.sse.2025.109083","url":null,"abstract":"<div><div>SiC power devices are suitable for high voltage and temperature applications due to their higher breakdown electrical field and thermal conductivity. Recently, many SiC SBDs and VDMOSFETs have been commercially produced. In comparison to Si-IGBT devices, the inherent body diode of SiC VDMOSFETs can also be used as the freewheeling diode in inductive switching power circuits, eliminating the need for an additional packaged diode. This can save costs and reduce the footprint of the total package. However, the bipolar carrier conduction and minority carrier injection mechanism on the body diode of SiC VDMOSFETs result in a higher turn-on knee voltage and longer reverse recovery time when used as a freewheeling diode. In fact, SiC SBDs are often utilized to replace the body diode, aiming to enhance the knee voltage and reverse recovery speed. To harness both the benefits of SiC VDMOSFETs and SBDs, it is worthwhile to integrate these two types of power devices into a single monolithic chip. In this study, we fabricated integrated JBS diodes into VDMOSFETs (JBSFETs) targeting 1700 V applications. Well-behaved JBSFETs with a threshold voltage (V<sub>th</sub>) of 1.9 V, specific on-resistance (R<sub>on,sp</sub>) of 5.2 mΩ-cm<sup>2</sup>, and acceptable blocking voltage (BV) of 2373 V have been achieved. The temperature dependence of the JBSFET device characteristics was also investigated. These results represent significant progress in implementing high-performance JBSFETs in power electronics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109083"},"PeriodicalIF":1.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impacts of trench angle on the performance of trench super-junction vertical double-diffused metal-oxide-semiconductor

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-11 DOI: 10.1016/j.sse.2025.109086

Yongjia Li , Di Gui , Feilu Chen , Wangran Wu , Weifeng Sun

引用次数: 0

Degradation mechanisms for static and dynamic characteristics in 1.2 kV 4H-SiC MOSFETs under repetitive short-circuit tests

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-11 DOI: 10.1016/j.sse.2025.109082

Ying Ji , Linna Zhao , Shilong Yang , Cunli Lu , Xiaofeng Gu , Wai Tung Ng

{"title":"Degradation mechanisms for static and dynamic characteristics in 1.2 kV 4H-SiC MOSFETs under repetitive short-circuit tests","authors":"Ying Ji , Linna Zhao , Shilong Yang , Cunli Lu , Xiaofeng Gu , Wai Tung Ng","doi":"10.1016/j.sse.2025.109082","DOIUrl":"10.1016/j.sse.2025.109082","url":null,"abstract":"<div><div>In this paper, repetitive short-circuit (RSC) tests are conducted at off-state and on-state gate-source voltages (<em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub>) of −4/+15 V, −4/+19 V and 0/+19 V, respectively, to investigate the degradation behaviors of 1.2 kV 4H-SiC MOSFETs. Combining experimental and simulation results, it is found that trapped electrons or holes in the gate oxide during the avalanche process are the main degradation mechanism for the static parameters. This results in increases of 0.4 V and 3.0 mΩ in <em>V</em><sub>TH</sub> and <em>R</em><sub>DS,ON</sub>, respectively, at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = −4/+19 V; 0.45 V and 4.1 mΩ at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = 0/+19 V; and decreases of 0.69 V and 3.2 mΩ at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = −4/+15 V after 240 short-circuit (SC) tests. The dynamic characteristics of the device under test, including <em>C</em><sub>GS</sub>, <em>C</em><sub>DS</sub>, <em>C</em><sub>GD</sub> also degrade. The trapped holes in the gate oxide above the JFET region lead to a thinner depletion region and an obvious increase in <em>C</em><sub>GD</sub>. Furthermore, the gate leakage current under high reverse gate bias is affected by the RSC tests, primarily attributed to trapped electrons hopping to the poly-Si/SiO<sub>2</sub> interface via defect states.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109082"},"PeriodicalIF":1.4,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-11 DOI: 10.1016/j.sse.2025.109081

Jen-Hao Chen , Fredo Chavez , Chien-Ting Tung , Sourabh Khandelwal , Chenming Hu

{"title":"A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies","authors":"Jen-Hao Chen , Fredo Chavez , Chien-Ting Tung , Sourabh Khandelwal , Chenming Hu","doi":"10.1016/j.sse.2025.109081","DOIUrl":"10.1016/j.sse.2025.109081","url":null,"abstract":"<div><div>A I-V and C-V parameter extraction methodology with various gate lengths utilizing a multi-stage neural network is proposed. This multi-stage neural network contains four networks focusing on extracting parameters from four different regions in transistor’s characteristics, enabling a machine to emulate human’s parameter extraction strategy. This methodology begins with the generation of a training dataset through Monte Carlo simulation, varying 53 selected IV and CV BSIM-CMG model parameters. With each Monte Carlo-selected parameter set, the I-V, transconductance, output conductance and C-V characteristics of seven different GAAFETs with different gate lengths ranging from 9 nm to 389 nm are generated. This multi-stage neural network is trained with the GAAFETs’ characteristics as the input and the 53 model parameters as the output. After training, TCAD-generated GAAFET I-V, conductance and C-V data with various gate lengths are used to test this neural network parameter extractor’s ability of extracting BSIM-CMG model parameters that generate data accurately fitting the TCAD IV and CV data. It is demonstrated that this parameter extraction neural network can extract BSIM-CMG model parameters’ value for GAAFETs within few seconds.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109081"},"PeriodicalIF":1.4,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-04 DOI: 10.1016/j.sse.2025.109080

A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez

{"title":"Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling","authors":"A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez","doi":"10.1016/j.sse.2025.109080","DOIUrl":"10.1016/j.sse.2025.109080","url":null,"abstract":"<div><div>The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109080"},"PeriodicalIF":1.4,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143377726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of the mobility behavior of MOS2 2D FETs

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109032

Antonio Cerdeira , Magali Estrada , Ahmed Mounir , Tibor Grasser , Benjamín Iñiguez

引用次数: 0