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Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding 等离子体处理对硅片和杂化键合SiO2表面和键合性能的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-16 DOI: 10.1016/j.sse.2025.109246
Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee
{"title":"Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding","authors":"Sung-Min Park ,&nbsp;Sang Hyun Jung ,&nbsp;Joong-Heon Kim ,&nbsp;Seung Heon Shin ,&nbsp;Jaejin Lee","doi":"10.1016/j.sse.2025.109246","DOIUrl":"10.1016/j.sse.2025.109246","url":null,"abstract":"<div><div>We investigate the effects of plasma on SiO<sub>2</sub> surfaces in various plasma environments, including Ar, O<sub>2</sub>, and N<sub>2</sub>, under identical plasma conditions for low-temperature annealing in SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding. After plasma treatments, no damage is observed on the SiO<sub>2</sub> surface, which is comparable to post-CMP SiO<sub>2</sub>. With the Ar and O<sub>2</sub> plasma treatments and XPS analysis, the SiO<sub>2</sub> surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N<sub>2</sub> plasma treatment results in a few isolated voids being observed compared to O<sub>2</sub> plasma treatment, N<sub>2</sub> plasma treatment will be a suitable choice for Cu/SiO<sub>2</sub> hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O<sub>2</sub> plasma treatment on SiO<sub>2</sub> surface is the most effective way for SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109246"},"PeriodicalIF":1.4,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High blocking voltage and low on-state voltage drop 4H-SiC p-channel IGBTs with optimized multizone floating field rings 具有优化的多区浮场环的4H-SiC p沟道igbt高阻塞电压和低导通电压降
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-12 DOI: 10.1016/j.sse.2025.109248
Ruixue Mai , Xiaoli Tian , Xinyu Liu , Xinhua Wang , Yun Bai , Wei Wei , Yuhao Guo , Chengyue Yang , Chengzhan Li , Yidan Tang
{"title":"High blocking voltage and low on-state voltage drop 4H-SiC p-channel IGBTs with optimized multizone floating field rings","authors":"Ruixue Mai ,&nbsp;Xiaoli Tian ,&nbsp;Xinyu Liu ,&nbsp;Xinhua Wang ,&nbsp;Yun Bai ,&nbsp;Wei Wei ,&nbsp;Yuhao Guo ,&nbsp;Chengyue Yang ,&nbsp;Chengzhan Li ,&nbsp;Yidan Tang","doi":"10.1016/j.sse.2025.109248","DOIUrl":"10.1016/j.sse.2025.109248","url":null,"abstract":"<div><div>A novel multizone floating field ring (M−FFR) edge termination structure with individually increasing ring spacing has been proposed, fabricated, and measured for 4H-silicon carbide (4H-SiC) p-channel insulated gate bipolar transistors (IGBTs). This M−FFR design effectively suppresses electric field crowding at the termination edge while maintaining a high tolerance to oxide charge accumulation. Numerical simulations indicate that the M−FFR achieves a 17.4 % higher blocking voltage compared to conventional equidistant floating field ring (Con-FFR) designs. Importantly, the proposed structure requires no complex fabrication steps or additional lithography processes, reducing manufacturing cost and complexity. To further enhance device performance, carrier lifetime enhancement techniques were applied to reduce the on-state voltage drop (<em>V</em><sub>f</sub>). Experimental measurements confirm that the fabricated p-channel SiC IGBTs are capable of sustaining blocking voltages exceeding 10 kV with leakage currents below 300nA. At a gate voltage of −20 V, a <em>V</em><sub>f</sub> of 5.77 V and a low differential specific on-resistance (<em>R</em><sub>on,sp,diff</sub>) of 17.5 mΩ·cm<sup>2</sup> were achieved. These results suggest that the device is promising for applications in high-power electronic devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109248"},"PeriodicalIF":1.4,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Layout effects on the thermal metrics of multichannel FinFETs 布局对多通道finfet热度量的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-12 DOI: 10.1016/j.sse.2025.109229
Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi
{"title":"Layout effects on the thermal metrics of multichannel FinFETs","authors":"Lisa Tondelli ,&nbsp;Andries J. Scholten ,&nbsp;Thanh Viet Dinh ,&nbsp;Luca Selmi","doi":"10.1016/j.sse.2025.109229","DOIUrl":"10.1016/j.sse.2025.109229","url":null,"abstract":"<div><div>FinFET technology is widely used for advanced digital, RF, and analog applications due to its high performance and scalability. However, the non-planar architecture introduces increased electrical parasitics and self-heating effects (SHEs), which can degrade device reliability and performance.</div><div>We analyze, by simulation, the thermal behavior of four FinFET layouts designed with realistic process rules, focusing on transistor channels at the boundary of the large FinFET arrays required by RF applications. The findings highlight key thermal trade-offs of FinFET structures and suggest ways to balance static and dynamic self-heating for optimum performance and limited overtemperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109229"},"PeriodicalIF":1.4,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An understanding of fracture kinetics during the layer transfer of InP InP层间传递过程中断裂动力学的认识
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-10 DOI: 10.1016/j.sse.2025.109240
K. Blanco , F. Mazen , T. Salvetat , D. Landru , F. Rieutord
{"title":"An understanding of fracture kinetics during the layer transfer of InP","authors":"K. Blanco ,&nbsp;F. Mazen ,&nbsp;T. Salvetat ,&nbsp;D. Landru ,&nbsp;F. Rieutord","doi":"10.1016/j.sse.2025.109240","DOIUrl":"10.1016/j.sse.2025.109240","url":null,"abstract":"<div><div>The layer transfer of InP with the Smart Cut™ technology shows an original behavior, with the existence of a transition temperature, above which fracture occurs rapidly and below which it never spontaneously happens. Using microcracks observation and measurement of the amount of H<sub>2</sub> inside cracks, we show that the existence of the two regimes is due to a competition between a trapping of implanted hydrogen inside the cracks and its out-diffusion into the bonded structure.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109240"},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Extraction of trap densities in Al:HfO2 MIM capacitors using voltage ramp stress measurements 利用电压斜坡应力测量提取Al:HfO2 MIM电容器中的陷阱密度
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-10 DOI: 10.1016/j.sse.2025.109239
Corinna Fohn , Emmanuel Chery , Kristof Croes , Michele Stucchi , Valeri Afanas’ev
{"title":"Extraction of trap densities in Al:HfO2 MIM capacitors using voltage ramp stress measurements","authors":"Corinna Fohn ,&nbsp;Emmanuel Chery ,&nbsp;Kristof Croes ,&nbsp;Michele Stucchi ,&nbsp;Valeri Afanas’ev","doi":"10.1016/j.sse.2025.109239","DOIUrl":"10.1016/j.sse.2025.109239","url":null,"abstract":"<div><div>We present an experimental method to directly evaluate the oxide trap densities in TiN/Al:HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>/TiN capacitors from the low-field current hysteresis in voltage-ramp-stress (VRS) measurements. The extracted densities of deep electron traps are in the 10<sup>13</sup> cm<sup>−2</sup> range and virtually independent of the Al-doping concentration in HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> (ranging from 2% to 20%). These results indicate that the trapping sites are intrinsic and may be related to polaronic states in disordered HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>. Regarding reproducibility and stability, the measurements were consistent across all samples, except for those with low Al doping, which exhibited increased leakage and degradation likely due to partial crystallization. In degraded samples, conductive paths formed after electrical stress confine the leakage, limiting the sensitivity of the method to local trap densities adjacent to the leakage path.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109239"},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of bottom channel coverage ratio on electrical characteristics of GAA Si NS CFETs for Sub-1-nm nodes 底部通道覆盖率对亚1nm节点GAA Si NS cfet电特性的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-08 DOI: 10.1016/j.sse.2025.109244
Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li
{"title":"Impact of bottom channel coverage ratio on electrical characteristics of GAA Si NS CFETs for Sub-1-nm nodes","authors":"Min-Hui Chuang ,&nbsp;Sekhar Reddy Kola ,&nbsp;Yiming Li","doi":"10.1016/j.sse.2025.109244","DOIUrl":"10.1016/j.sse.2025.109244","url":null,"abstract":"<div><div>This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both <em>n</em> on <em>p</em> and <em>p</em> on <em>n</em> stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (<em>p</em> on <em>n</em>) and 140× (<em>n</em> on <em>p</em>) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109244"},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145019791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flexible & light-weight III-V concentrated photovoltaics for automobile application 柔性和轻便的III-V型聚光光伏汽车应用
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-06 DOI: 10.1016/j.sse.2025.109243
Sahil Sharma , Kumaran Selva , Carlos A. Favela , Bo Yu , Venkat Selvamanickam
{"title":"Flexible & light-weight III-V concentrated photovoltaics for automobile application","authors":"Sahil Sharma ,&nbsp;Kumaran Selva ,&nbsp;Carlos A. Favela ,&nbsp;Bo Yu ,&nbsp;Venkat Selvamanickam","doi":"10.1016/j.sse.2025.109243","DOIUrl":"10.1016/j.sse.2025.109243","url":null,"abstract":"<div><div>Use of solar energy for electric power has a huge potential to reduce the carbon footprint caused by greenhouse gases (GHG). While photovoltaics (PV) has been adopted in mainstream terrestrial applications, their implementation in the automotive sector, to make PV-powered vehicles, has been minimal. The existing PV-powered vehicles utilize low-efficiency solar cells, which limits the driving range to 20 miles/day. In this work, we present concentrated photovoltaic (CPV) devices using high-efficiency III-V solar cells for automobile application to realize longer driving range. We have developed inexpensive and flexible III-V PV on metal tapes and integrated them with a durable, flexible PDMS microlens for light concentration. The integrated device showed more than 9 times improvement in current density and power output compared to a solar device without a light concentrator at 1 sun. Use an array of microlens integrated with III-V PV could extend the driving range to 115 miles/day for a vehicle with an electric mileage of 10 miles/kWh. We have also investigated the effect of the light incident angle on device performance to evaluate the optimal tilt angle while mounting the PV module on the vehicle’s roof.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109243"},"PeriodicalIF":1.4,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon nanowire field-effect transistor biosensors with bowtie antenna 带领结天线的硅纳米线场效应晶体管生物传感器
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-06 DOI: 10.1016/j.sse.2025.109230
Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich
{"title":"Silicon nanowire field-effect transistor biosensors with bowtie antenna","authors":"Yongqiang Zhang ,&nbsp;Kai Li ,&nbsp;Nazarii Boichuk ,&nbsp;Denys Pustovyi ,&nbsp;Valeriia Chekubasheva ,&nbsp;Hanlin Long ,&nbsp;Mykhailo Petrychuk ,&nbsp;Svetlana Vitusevich","doi":"10.1016/j.sse.2025.109230","DOIUrl":"10.1016/j.sse.2025.109230","url":null,"abstract":"<div><div>In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl<sub>2</sub> solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109230"},"PeriodicalIF":1.4,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model 基于斯坦福模型的基于氧化物的电阻随机存取存储单元编程的封闭模型
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-09-03 DOI: 10.1016/j.sse.2025.109238
Nadine Dersch , Eduardo Perez , Christian Wenger , Mike Schwarz , Benjamin Iniguez , Alexander Kloes
{"title":"A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model","authors":"Nadine Dersch ,&nbsp;Eduardo Perez ,&nbsp;Christian Wenger ,&nbsp;Mike Schwarz ,&nbsp;Benjamin Iniguez ,&nbsp;Alexander Kloes","doi":"10.1016/j.sse.2025.109238","DOIUrl":"10.1016/j.sse.2025.109238","url":null,"abstract":"<div><div>This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109238"},"PeriodicalIF":1.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145010667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications 基于3nm IRDS投影的无结叉片FET设计空间可变性和实验可行性:对下一代数字、模拟/RF和电路应用的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-31 DOI: 10.1016/j.sse.2025.109231
Kavya Mulaga , Mohan Siva Kumar Mattaparthi , Ramya Dalai , Sresta Valasa , Venkata Ramakrishna Kotha , Sunitha Bhukya , Narendar Vadthiya
{"title":"A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications","authors":"Kavya Mulaga ,&nbsp;Mohan Siva Kumar Mattaparthi ,&nbsp;Ramya Dalai ,&nbsp;Sresta Valasa ,&nbsp;Venkata Ramakrishna Kotha ,&nbsp;Sunitha Bhukya ,&nbsp;Narendar Vadthiya","doi":"10.1016/j.sse.2025.109231","DOIUrl":"10.1016/j.sse.2025.109231","url":null,"abstract":"<div><div>This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (L<sub>g</sub>), width (W<sub>FS</sub>), and thickness (T<sub>FS</sub>) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of L<sub>g</sub> = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of L<sub>g</sub> &gt; 12 nm is not suitable for designed JL-FSFET since it gives deteriorated A<sub>v</sub> and f<sub>T</sub> which are the primary performance metrics to boost the device performance. Additionally, lowering the W<sub>FS</sub> and T<sub>FS</sub> is an optimal choice for improving the digital and analog performance whereas higher W<sub>FS</sub> and T<sub>FS</sub> should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised A<sub>v</sub> whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (L<sub>g</sub> = 12 nm, T<sub>FS</sub> = 5 nm, W<sub>FS</sub> = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109231"},"PeriodicalIF":1.4,"publicationDate":"2025-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144933520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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