Solid-state Electronics最新文献_第2页

Carrier modulation and effective passivation of tin oxide thin-film transistors by organic surface doping 通过有机表面掺杂实现氧化锡薄膜晶体管的载流子调制和有效钝化

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-16 DOI: 10.1016/j.sse.2024.109005

引用次数: 0

Fine-tuning Cesium lead chloride perovskite field-effect transistors for sensing applications: Bridging numerical modeling and experimental validation 微调用于传感应用的氯化铯铅过氧化物场效应晶体管：连接数值建模与实验验证

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-12 DOI: 10.1016/j.sse.2024.109004

{"title":"Fine-tuning Cesium lead chloride perovskite field-effect transistors for sensing applications: Bridging numerical modeling and experimental validation","authors":"","doi":"10.1016/j.sse.2024.109004","DOIUrl":"10.1016/j.sse.2024.109004","url":null,"abstract":"<div>This study presents a comprehensive approach to fine-tuning Cesium Lead Chloride Perovskite Field-Effect Transistors (CsPbCl3-FETs) for sensing applications by bridging numerical modeling with experimental validation. By combining finite element methods in COMSOL Multiphysics for optimization, we tailored FET parameters such as oxide and perovskite thin film thickness. The fabricated FET, with a 200 nm semiconductor layer and 30 nm oxide thickness, was strategically chosen to operate in a non-depletion mode, maximizing mobility while minimizing power consumption. Experimental results closely aligned with numerical simulations, showcasing a threshold voltage of 0.50 V±0.07 V and an impressive on/off current ratio of 1.50 x 104 ± 0.3 x 104. Notably, the perovskite FET exhibited remarkable carrier mobility in saturation mode, reaching 5.40 cm2/V-s ± 0.8 cm2/V-s, outperforming other attempts in the literature. This work underscores the potential of CsPbCl3 FETs for high-performance sensing applications, offering insights into optimizing device parameters for enhanced functionality and efficiency.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142233637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect 包含准饱和效应的改进型碳化硅功率 MOSFET 温度可变直流模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-08-12 DOI: 10.1016/j.sse.2024.108993

{"title":"Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect","authors":"","doi":"10.1016/j.sse.2024.108993","DOIUrl":"10.1016/j.sse.2024.108993","url":null,"abstract":"<div>In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141990468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel method to determine bias-dependent source and drain parasitic series resistances in AlGaN/GaN high electron mobility transistors 确定氮化铝/氮化镓高电子迁移率晶体管中与偏置有关的源极和漏极寄生串联电阻的新方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-08-02 DOI: 10.1016/j.sse.2024.108991

{"title":"A novel method to determine bias-dependent source and drain parasitic series resistances in AlGaN/GaN high electron mobility transistors","authors":"","doi":"10.1016/j.sse.2024.108991","DOIUrl":"10.1016/j.sse.2024.108991","url":null,"abstract":"<div>The AlGaN/GaN high electron mobility transistors (HEMTs) with T-gate that suitable for high frequency applications were fabricated. A novel method to extract the bias-dependent source and drain parasitic series resistances (Rs and Rd) of AlGaN/GaN HEMTs is proposed. By analyzing the distributed capacitance and current generator network in the velocity saturated regions of the AlGaN/GaN HEMTs, a new restriction relationship between small-signal equivalent circuit elements is found. The Rs and Rd can be determined under active bias through wideband S-parameter measurements, which can better reflect the physical mechanism of AlGaN/GaN HEMTs under normal operation. The S-parameters and extrinsic transconductance calculated based the small-signal equivalent circuit element values extracted by the method proposed in this paper are very consistent with the experimental values, which reflects the accuracy of this element extraction method. In this paper, the physical mechanism that causes Rs and Rd to vary with bias voltage is also studied. This study has a deeper insight into the bias-dependence of Rs and Rd, which modifies the understanding for physical mechanisms of AlGaN/GaN HEMTs. The research results provide new ideas for establishing small-signal equivalent circuit models containing more physical effects and is of great significance to GaN-based integrated circuit design.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The study on influence factors of contact properties of metal-MoS2 interfaces 金属-MoS2界面接触性能影响因素研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-30 DOI: 10.1016/j.sse.2024.108992

{"title":"The study on influence factors of contact properties of metal-MoS2 interfaces","authors":"","doi":"10.1016/j.sse.2024.108992","DOIUrl":"10.1016/j.sse.2024.108992","url":null,"abstract":"<div>The metal and two-dimension (2D) semiconductor contact interfaces have a more considerable contact resistance hindering carrier injection, which makes the performance of 2D semiconductor devices less than the theory. The contact properties of Ni, Au, and Mo with MoS2 are simulated by the first-principles method. The interface dipole caused by the interface charge redistribution changes the work function difference at the metal-MoS2 interface, so the interface charge redistribution is one of the important factors for correctly evaluating the contact properties. Due to the metal-induced gap states (MIGS) at metal-monolayer (ML) MoS2 interfaces, the Fermi level is strongly pinned to fixed energy, and the Schottky barrier height (SBH) cannot be regulated efficiently by the metal work function. Although the work function of Au is bigger than Ni, the Fermi level of Au is pinned at a higher position. In the meantime, the bandgap of MoS2 narrows and metallization occurs due to the larger MIGS. In the Mo-MoS2 interface, the Fermi level is pinned near the conduction band minimum of MoS2. The contact resistances (Rc) of the three structures are tested by the Circular Transfer Length Method (CTLM), which is consistent with the prediction of the simulation. The Mo-MoS2 has the smallest Rc. The results indicate that contact resistance of 2D semiconductors cannot be simply predicted by soled work functions or Fermi level pinning, but is determined by several factors.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141961008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ANN-based framework for modeling process induced variation using BSIM-CMG unified model 利用 BSIM-CMG 统一模型，建立基于 ANN 的流程诱导变异建模框架

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-22 DOI: 10.1016/j.sse.2024.108988

引用次数: 0

A versatile compact model of resistive random-access memory (RRAM) 电阻式随机存取存储器（RRAM）的多功能紧凑型模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-15 DOI: 10.1016/j.sse.2024.108989

引用次数: 0

Improvement of electrical performance in Normally-Off GaN MOSFET with regrown AlGaN layer on the Source/Drain region 利用源极/漏极区的再生氮化铝层改善常关断氮化镓 MOSFET 的电气性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-14 DOI: 10.1016/j.sse.2024.108987

{"title":"Improvement of electrical performance in Normally-Off GaN MOSFET with regrown AlGaN layer on the Source/Drain region","authors":"","doi":"10.1016/j.sse.2024.108987","DOIUrl":"10.1016/j.sse.2024.108987","url":null,"abstract":"<div>A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and Lg of 10 μm shows enhanced electrical performance such as maximum drain current (ID,max) of 57 mA/mm, maximum transconductance (gm,max) of 11 mS/mm, and field-effect mobility (μFE) of 59 cm2/V·s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0038110124001369/pdfft?md5=59e372a1b6529a8bc762128c67a00206&pid=1-s2.0-S0038110124001369-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141637705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A composite model of memristors based on barrier and dopant drift mechanisms 基于势垒和掺杂漂移机制的忆阻器复合模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-14 DOI: 10.1016/j.sse.2024.108990

引用次数: 0

Degradation analysis of GaN-based high–electron-mobility transistors under different stresses in semi-on state conditions 半导通状态下不同应力作用下氮化镓基高电子迁移率晶体管的降解分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-06 DOI: 10.1016/j.sse.2024.108977

{"title":"Degradation analysis of GaN-based high–electron-mobility transistors under different stresses in semi-on state conditions","authors":"","doi":"10.1016/j.sse.2024.108977","DOIUrl":"10.1016/j.sse.2024.108977","url":null,"abstract":"<div>The large numbers of high-energy carriers that occur in semiconductor devices under semi-on state conditions can cause significant device degradation. The effects of different stresses on the electrical and trapping characteristics of GaN-based high-electron-mobility transistors (HEMTs) are investigated. Test results for GaN HEMTs under semi-on state conditions show that the electrical characteristics of these devices degrade to a certain extent after they are subjected to electrical pulse stress cycles with different drain voltage, frequencies, and duty cycles; a degree of degradation also occurs in the electrical characteristics of the devices when they are subjected to direct current electrical stresses. After electrical stress is applied, the absolute amplitude of the traps in the device increases, thus indicating an increase in the trap density. The results show that voltage is the main driver for device damage, with the current playing an accelerating role through its effects on device temperature or by supplying hot electrons; therefore, the drain voltage has the most significant effect on device degradation, which is mainly due to channel high-energy hot electron injection.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141637704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0