Solid-state Electronics最新文献_第2页

Exploring low-k/high-k multilayers as high breakdown strength dielectrics for capacitors 探索低钾/高钾多层电容器的高击穿强度介质

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2026-01-15 DOI: 10.1016/j.sse.2026.109331

Julie Chaussard , Chloé Guérin , Aude Lefèvre , Patrice Gonon , Vincent Jousseaume

引用次数: 0

Corrigendum to “1T-DRAM with retrograde doping” [Solid-State Electron. 232 (2026) 109315] “1T-DRAM与逆行掺杂”的勘误表[固态电子，232 (2026)109315]

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2026-01-16 DOI: 10.1016/j.sse.2025.109328

Maki Ulla , M.D. Yasir Bashir , Mohammad Jawaid Siddiqui

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Design, Synthesis, and Optoelectronic Characterization of a Novel Cu(II) Complex-Based Photodiode with Prof. Dr. Yakuphanoglu’s Advanced Fytronix Solar Simulator Characterization Techniques 基于Yakuphanoglu教授先进的Fytronix太阳模拟器表征技术的新型Cu（II）配合物光电二极管的设计、合成和光电表征

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2025-12-02 DOI: 10.1016/j.sse.2025.109311

Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu

{"title":"Design, Synthesis, and Optoelectronic Characterization of a Novel Cu(II) Complex-Based Photodiode with Prof. Dr. Yakuphanoglu’s Advanced Fytronix Solar Simulator Characterization Techniques","authors":"Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu","doi":"10.1016/j.sse.2025.109311","DOIUrl":"10.1016/j.sse.2025.109311","url":null,"abstract":"<div><div>In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage <em>(I-V)</em> characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity <em>(R)</em> and detectability <em>(D*)</em> values of the photodiode were measured as 2.9 mA/W and 1.95 × 10<sup>13</sup> Jones, respectively, at an illumination intensity of 80 mW/cm<sup>2</sup>. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109311"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Short-term charge trapping effects in ferroelectric FETs: impact of pulse amplitude and timing 铁电场效应管中的短期电荷俘获效应：脉冲振幅和时序的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2026-01-11 DOI: 10.1016/j.sse.2026.109332

Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick

{"title":"Short-term charge trapping effects in ferroelectric FETs: impact of pulse amplitude and timing","authors":"Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick","doi":"10.1016/j.sse.2026.109332","DOIUrl":"10.1016/j.sse.2026.109332","url":null,"abstract":"<div><div>This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 nm bulk high-k metal gate (HKMG) technology.</div><div>Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.</div><div>A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.</div><div>Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.</div><div>The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109332"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously PVE和IPF同时诱导GAA Si NS cfet的射频变异性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2025-12-30 DOI: 10.1016/j.sse.2025.109326

Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li

{"title":"Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously","authors":"Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li","doi":"10.1016/j.sse.2025.109326","DOIUrl":"10.1016/j.sse.2025.109326","url":null,"abstract":"<div><div>Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (<em>PVE</em>) and intrinsic parameter fluctuations (<em>IPF</em>). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (<em>T<sub>NS</sub></em>), width (<em>W<sub>NS</sub></em>), and gate length (<em>L<sub>G</sub></em>)—play a pivotal role in shaping intrinsic resistance (<em>r<sub>o</sub></em>), output resistance (<em>R<sub>out</sub></em>), voltage gain (<em>A<sub>V</sub></em>), cut-off frequency (<em>f<sub>T</sub></em>), and 3-dB bandwidth (<em>f</em><sub>3</sub><em><sub>dB</sub></em>), due to their influence on surface potential profiles and carrier transport behavior. Notably, within <em>IPF</em>, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (<em>WKF</em>) strongly perturb the channel surface potential, thereby inducing significant variability in <em>A<sub>V</sub></em>, <em>f<sub>T</sub></em>, <em>f</em><sub>3</sub><em><sub>dB</sub></em>, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of <em>PVE</em> and <em>IPF</em>. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109326"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Difference in kinetics between thermal nitridation and radical nitridation processes of 4H-SiC surface considering simultaneous N-incorporation and N-desorption reactions 考虑n -吸附和n -脱附反应的4H-SiC表面热氮化和自由基氮化过程动力学差异

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-04-01 Epub Date: 2026-01-20 DOI: 10.1016/j.sse.2026.109334

Haruki Yoshida, Takashi Onaya, Atsushi Tamura, Koji Kita

引用次数: 0

Modeling of tunneling through Schottky barriers 通过肖特基屏障的隧道建模

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-02-01 Epub Date: 2025-11-29 DOI: 10.1016/j.sse.2025.109295

Bogdan Majkusiak

引用次数: 0

Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors 单界面陷阱位置对无结纳米线晶体管低频噪声的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-02-01 Epub Date: 2025-11-30 DOI: 10.1016/j.sse.2025.109305

Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria

{"title":"Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors","authors":"Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109305","DOIUrl":"10.1016/j.sse.2025.109305","url":null,"abstract":"<div><div>This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (<em>V<sub>GS</sub></em>) at a low drain-to-source voltage (<em>V<sub>DS</sub></em>) to observe its direct effect on the current noise spectral density (<em>S<sub>id</sub></em>), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The <em>S<sub>id</sub></em> extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing S<sub>id</sub> with higher V<sub>GS</sub>, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct <em>S<sub>id</sub></em> trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109305"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration 用简单的1T1R结构改善基于hfo2的RRAM的模拟开关行为

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-02-01 Epub Date: 2025-12-08 DOI: 10.1016/j.sse.2025.109314

Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang

{"title":"Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration","authors":"Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang","doi":"10.1016/j.sse.2025.109314","DOIUrl":"10.1016/j.sse.2025.109314","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109314"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Progress towards integration of MTJ devices with cryo-CMOS readout circuitry for magnetic field sensing 磁场感应MTJ器件与低温cmos读出电路集成的进展

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-02-01 Epub Date: 2025-12-02 DOI: 10.1016/j.sse.2025.109312

Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky

引用次数: 0