Impact of Device Layout on Self-Heating Extraction in MOSFETs

This work analyses the impact of device layout on self-heating (SH) extraction and treats it in terms of parasitic series resistance and heat evacuation paths. Specifically, the impact of having four-terminal (4T) gate access structures used in gate resistance technique for SH characterization is investigated. To evaluate the SH parameters, the RF characterization technique is utilized, which includes measuring S-parameters over a wide frequency range. Two devices are compared in this study based on the same core MOSFET: one with the 4T gate access structure and one without these additional accesses. It is experimentally demonstrated that a lower thermal resistance is observed for the 4T device. Apart from cooling through the 4T gate accesses which could explain this observation, it is seen that parasitic series resistances could also affect the extraction of thermal resistance through the RF technique. Through PDK simulations, the impact of the series resistances on SH extraction using the RF technique is explored further. The fact that even for the same core device the layout can affect the extracted thermal parameters is evidenced.